FT4222HQ-C-R datasheet(22/49 Pages) FTDI

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FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC

1.3

Document No.: FT_001011 Clearance No.: FTDI#405

Parameter

Min(ns)

Typ(ns)

Max(ns)

Description

T0@48MHz

20.833

T0 is the period when operating clock=48MHz

T0@60MHz

16.666

T0 is the period when operating clock=60MHz

T0@80MHz

12.500

T0 is the period when operating clock=80MHz

Timing for I2C Master

T1@SM

16*T0

8*(1+N)*T0

SCK Period when I2C as master with standard

speed mode(SM)

T1@FM/HM

12*T0

6*(1+N)*T0

SCK Period when I2C as master with FM, FM+,

HS speed mode

8*T0

4*(1+N)*T0

SCK high pulse width when I2C as master with

standard speed mode(SM)

4*T0

2*(1+N)*T0

SCK high pulse width when I2C as master with

FM, FM+, HS speed mode

2*(1+N)*T0

SDA output setup time to SCL rising edge when

I2C as master

2*(1+N)*T0

SDA output hold time to SCL falling edge when

I2C as master

＞＝

input setup time requirement from SDA to SCL

rising edge when I2C as master

＞＝

input hold time requirement from SDA to SCL

falling edge when I2C as master

2*(1+N)*T0

Start bit setup time to SCL falling edge

4*(1+N)*T0

Start bit hold time to SCL falling edge

2*(1+N)*T0

Stop bit setup time to SCL rising edge

T10

2*(1+N)*T0

Stop bit hold time to SCL rising edge

T11

4*(1+N)*T0

Bus free time between Start and Stop bit

Timing for I2C Slave

12*T0

Acceptable SCL Period when I2C as slave device

1*T0

SCL high pulse width requirement when I2C as

slave

＞＝

input setup time requirement from SDA to SCL

rising edge when I2C as slave device

1*T0

input hold time requirement from SDA to SCL

falling edge when I2C as slave device

T8 - T6

SDA output setup time to SCL rising edge

3*T0

4*T0

5*T0

SDA output hold time to SCL falling edge

Table 5.4 I2C Timing for VCCIO=3.3V

Note that N can be ranged from 1 to 255

FT4222HQ-C-R Datasheet(PDF) 22 Page - Future Technology Devices International Ltd.

FT4222HQ-C-R Datasheet(HTML) 22 Page - Future Technology Devices International Ltd.

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