PC87360 datasheet(103/168 Pages) NSC

103 / 168 page

3.0 System Wake-Up Control (SWC) (Continued)

103

www.national.com

3.4.30

Standby GPIO Pin Configuration Register (SBGPCFG)

This is a group of eight identical configuration registers, each of which is associated with one GPIOE/GPIE pin. The entire

set is mapped to the same address. The mapping scheme is based on the Standby GPIO Pin Select (SBGPSEL) register

that functions as an index register, and the specific Standby GPIO Pin Configuration register that reflects the configuration

of the currently selected pin.

Bits 0-3 are applicable only for pins GPIOE0-5. Bits 4-6 are applicable for all GPIOE/GPIE pins.

Location:

Bank 3, Offset 14h

Type:

R/W (bit 3 is set only)

For GPIOE and GPIE:

Bit

76543210

Name

Reserved

Event

Debounce

Enable

Event

Polarity

Event Type

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

01000100

Bit

Description

Reserved

Event Debounce Enable

0: Disabled

1: Enabled (default)

Event Polarity. This bit deﬁnes the polarity of the signal that causes a detection of an event from the

corresponding GPIO pin.

0: Falling edge or low level input (default)

1: Rising edge or high level input

Event Type. This bit deﬁnes the signal type that causes a detection of an event from the corresponding GPIO

pin.

0: Edge input (default)

1: Level input

Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by

the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by VSB power-up reset.

0: No effect (default at VSB power-up reset)

1: Direction, output type, pull-up and output value locked

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals.

0: Disabled

1: Enabled (default)

Output Type. This bit controls the output buffer type (open-drain or totem pole) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. For GPIOE and GPIE, this bit indicates the GPIO pin output state. It has no effect on input.

0: TRI-STATE (default for GPIOE/GPIE)

1: Output enabled

PC87360 Datasheet(PDF) 103 Page - National Semiconductor (TI)

PC87360 Datasheet(HTML) 103 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL