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TNETV2664FIBZWT Datasheet(PDF) 17 Page - Texas Instruments |
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TNETV2664FIBZWT Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 31 16 RESERVED R-0000 0000 0000 0000 15 3 2 0 RESERVED L1PMODE R- 0000 0000 0000 0 R/W-111 (7h) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. Figure 2-4. L1PCFG Register Table 2-3. L1PCFG Register Description Bit Field Name Description 31:3 RESERVED Reserved. Read-only, writes have no effect. L1PMODE select. 000 [0h] = L1P Cache Disabled 001 [1h] = 4 KB 010 [2h] = 8 KB 2:0 L1PMODE 011 [3h] = 16KB 100 [4h] = 32KB 101 [5h] = 32KB 110 [6h] = 32KB 111 [7h] = 32KB [default]. 2.2.2.2 L1D Configuration Register (L1DCFG) Description The L1D Configuration Register (L1DCFG) controls/defines the size of the L1D cache. On the C6424, the L1DCFG register is device-specific and varies from what is shown in the TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871). The format and bit field descriptions of the L1DCFG register for the C6424 are shown in Figure 2-5 and Table 2-4, respectively. 31 16 RESERVED R-0000 0000 0000 0000 15 3 2 0 RESERVED L1DMODE R- 0000 0000 0000 0 R/W-111 (7h) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. Figure 2-5. L1DCFG Register Table 2-4. L1DCFG Register Description Bit Field Name Description 31:3 RESERVED Reserved. Read-only, writes have no effect. L1DMODE select. 000 [0h] = L1D Cache Disabled 001 [1h] = 4 KB 010 [2h] = 8 KB 2:0 L1DMODE 011 [3h] = 16KB 100 [4h] = 32KB 101 [5h] = 32KB 110 [6h] = 32KB 111 [7h] = 32KB [default]. Copyright © 2007–2009, Texas Instruments Incorporated Device Overview 17 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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