TNETV2664FIBZWT datasheet(52/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 2-20. Multichannel Buffered Serial Port 0 and Multichannel Buffered Serial Port 1 (McBSP0 and

McBSP1) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

Multichannel Buffered Serial Port 0 (McBSP0)

For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.

CLKS0/TOUT0L/

IPD

This pin is multiplexed between McBSP0, Timer0, and GPIO.

I/O/Z

GP[97]

DVDD33

For McBSP0, it is McBSP0 external clock source (I).

ACLKR0/CLKX0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[99]

DVDD33

For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).

AHCLKR0/CLKR0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[101]

DVDD33

For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[2]/FSX0/

IPD

I/O/Z

For McBSP0, it is McBSP0 transmit frame synchronization FSX0

GP[103]

DVDD33

(I/O/Z).

This pin is multiplexed between McASP0, McBSP0, and GPIO.

AXR0[3]/FSR0/

IPD

I/O/Z

For McBSP0, it is McBSP0 receive frame synchronization FSR0

GP[102]

DVDD33

(I/O/Z).

AXR0[1]/DX0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[104]

DVDD33

For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).

AFSR0/DR0/

IPD

This pin is multiplexed between McASP0, McBSP0, and GPIO.

I/O/Z

GP[100]

DVDD33

For McBSP0, it is McBSP0 data receive input DR0 (I).

Multichannel Buffered Serial Port 1 (McBSP1)

For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.

CLKS1/TINP0L/

IPD

This pin is multiplexed between McBSP0, Timer0, and GPIO.

I/O/Z

GP[98]

DVDD33

For McBSP1, it is McBSP1 external clock source (I).

ACLKX0/CLKX1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[106]

DVDD33

For McBSP1, it is McBSP1 transmit clock CLKX1 (I/O/Z).

AHCLKX0/CLKR1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[108]

DVDD33

For McBSP1, it is McBSP1 receive clock CLKR1 (I/O/Z).

This pin is multiplexed between McASP0, McBSP1, and GPIO.

AMUTEIN0/FSX1/

IPD

I/O/Z

For McBSP1, it is McBSP1 transmit frame synchronization FSX1

GP[109]

DVDD33

(I/O/Z).

This pin is multiplexed between McASP0, McBSP1, and GPIO.

AXR0[0]/FSR1/

IPD

I/O/Z

For McBSP1, it is McBSP1 receive frame synchronization FSR1

GP[105]

DVDD33

(I/O/Z).

AFSX0/DX1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[107]

DVDD33

For McBSP1, it is McBSP1 data transmit output DX1 (O/Z).

AMUTE0/DR1/

IPD

This pin is multiplexed between McASP0, McBSP1, and GPIO.

I/O/Z

GP[110]

DVDD33

For McBSP1, it is McBSP1 data receive input DR1 (I).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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