TNETV2664FIBZWT datasheet(40/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101)

Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEM[2:0], etc.). For more details, see

Section 3.7, Multiplexed Pin Configurations.

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[1]/(ALE)/

IPD

A16

B20

I/O/Z

When used for EMIFA (NAND) , this pin is the Address Latch Enable

GP[9]/(PLLMS1)

DVDD33

output (ALE).

This pin is multiplexed between EMIFA (NAND) and GPIO.

EM_A[2]/(CLE)/

IPD

B16

A20

I/O/Z

When used for EMIFA (NAND) , this pin is the Command Latch

GP[8]/(PLLMS0)

DVDD33

Enable output (CLE).

EM_WAIT/

IPU

E15

D20

I/O/Z

When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).

(RDY/BSY)

DVDD33

IPU

EM_OE

D15

D19

I/O/Z

When used for EMIFA (NAND), this pin is read enable output (RE).

DVDD33

IPU

EM_WE

E14

C19

I/O/Z

When used for EMIFA (NAND), this pin is write enable output (WE).

DVDD33

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use

with NAND flash.

EM_CS2/

IPD

This is the chip select for the default boot and ROM boot modes.

C19

C22

I/O/Z

GP[12]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMIFA (NAND) and GPIO.

For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use

with NAND flash.

EM_CS3/

IPD

C18

D22

I/O/Z

GP[13]

DVDD33

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and

GPIO.

For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with

RMRXD0/

IPD

NAND flash.

EM_CS4/

E19

H22

I/O/Z

DVDD33

GP[32]

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and

GPIO.

For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with

RMRXD1/

IPD

NAND flash.

EM_CS5/

F19

J22

I/O/Z

DVDD33

GP[33]

Note: This pin features an internal pulldown (IPD). If this pin is

connected and used as an EMIFA chip select signal, for proper device

operation, an external pullup resistor must be used to ensure the

EM_CSx function defaults to an inactive (high) state.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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