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TNETV2664FIBZWT Datasheet(PDF) 98 Page - Texas Instruments |
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TNETV2664FIBZWT Datasheet(HTML) 98 Page - Texas Instruments |
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98 / 249 page  TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com Table 3-19. Multiplexed Pins on C6424 (continued) SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. HD12/MTXD2/PPAR/GP[70] D5 C5 Host Block PCIEN, HOSTBK HD13/MTXD1/AD14/GP[71] B4 B4 Host Block PCIEN, HOSTBK HD14/MTXD0/AD15/GP[72] D4 B5 Host Block PCIEN, HOSTBK HD15/MTXCLK/AD12/GP[73] A4 A4 Host Block PCIEN, HOSTBK HHWIL/MRXDV/AD13/GP[74] C4 D3 Host Block PCIEN, HOSTBK HCNTL1/MTXEN/AD11/GP[75] D3 C4 Host Block PCIEN, HOSTBK HCNTL0/MRXER/AD10/GP[76] B3 B2 Host Block PCIEN, HOSTBK HR/W/MRXCLK/AD8/GP[77] A3 A3 Host Block PCIEN, HOSTBK HDS2/MRXD0/AD9/GP[78] C3 C2 Host Block PCIEN, HOSTBK HDS1/MRXD1/AD7/GP[79] B2 B3 Host Block PCIEN, HOSTBK HRDY/MRXD2/PCBE0/GP[80] D2 C3 Host Block PCIEN, HOSTBK HCS/MDCLK/AD5/GP[81] C1 D1 Host Block PCIEN, HOSTBK HINT/MRXD3/AD6/GP[82] C2 D2 Host Block PCIEN, HOSTBK HAS/MDIO/AD3/GP[83] D1 C1 Host Block PCIEN, HOSTBK AD0/GP[0] E1 E1 GPIO Block PCIEN AD1/GP[1] E2 E2 GPIO Block PCIEN AD2/GP[2] E3 F1 GPIO Block PCIEN AD4/GP[3] E4 F2 GPIO Block PCIEN GP[4]/PWM1 F3 F3 PWM1Block PWM1BK ACLKR0/CLKX0/GP[99] H1 J1 Serial Port Sub-Block 0 SPBK0 AFSR0/DR0/GP[100] H4 K3 Serial Port Sub-Block 0 SPBK0 AHCLKR0/CLKR0/GP[101] J2 K1 Serial Port Sub-Block 0 SPBK0 AXR0[3]/FSR0/GP[102] G4 J3 Serial Port Sub-Block 0 SPBK0 AXR0[2]/FSX0/GP[103] H3 J2 Serial Port Sub-Block 0 SPBK0 AXR0[1]/DX0/GP[104] J3 K2 Serial Port Sub-Block 0 SPBK0 AXR0[0]/FSR1/GP[105] H2 H2 Serial Port Sub-Block 1 SPBK1 ACLKX0/CLKX1/GP[106] F1 G1 Serial Port Sub-Block 1 SPBK1 AFSX0/DX1/GP[107] G2 G2 Serial Port Sub-Block 1 SPBK1 AHCLKX0/CLKR1/GP[108] G1 H1 Serial Port Sub-Block 1 SPBK1 AMUTEIN0/FSX1/GP[109] F2 G3 Serial Port Sub-Block 1 SPBK1 AMUTE0/DR1/GP[110] G3 H3 Serial Port Sub-Block 1 SPBK1 TINP1L/URXD1/GP[56] L4 P3 Timer 1 Block TIM1BK TOUT1L/UTXD1/GP[55] K4 N3 Timer 1 Block TIM1BK CLKS1/TINP0L/GP[98] K2 L2 Timer 0 Block TIM0BK CLKS0/TOUT0L/GP[97] J4 L3 Timer 0 Block TIM0BK URXD0/GP[85] L2 M2 UART0 Data Block UR0DBK UTXD0/GP[86] K3 N1 UART0 Data Block UR0DBK UCTS0/GP[87] L1 P1 UART0 Flow Control Block UR0FCBK URTS0/PWM0/GP[88] L3 M3 UART0 Flow Control Block UR0FCBK CLKOUT0/PWM2/GP[84] M1 R1 CLKOUT Block CKOBK Note: PINMUX groups EMIFA Sub-Block 2 and PCI Data Block are not shown in the above table because there is no actual pin multiplexing in those blocks. But these two blocks are still considered "pin mux blocks" because they contain some of the pins necessary for EMIFA and PCI, respectively. The pins in these blocks are as follows: • EMIFA Sub-Block 2 – EM_WAIT/(RDY/BSY) – EM_OE – EM_WE 98 Device Configurations Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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