R5F11BLE datasheet(54/143 Pages) RENESAS

54 / 143 page

RL78/G1F

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)

R01DS0246EJ0110 Rev. 1.10

Page 54 of 140

Aug 12, 2016

Note 1.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

Note 2.

Use it with EVDD0

≥ Vb.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 48-, 32-, 24-pin

products)/EVDD tolerance (for the 64-, 36-pin products)) mode for the SOp pin and SCKp pin by using port input

mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with

TTL input buffer selected.

(Remarks are listed on the page after the next page.)

(8)

Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output)

(TA = -40 to +85°C, 1.8 V

≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V)

(2/3)

Parameter

Symbol

Conditions

HS (high-speed main)

mode

LS (low-speed main)

mode

LV (low-voltage main)

mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SIp setup time

(to SCKp↑) Note 1

tSIK1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

479

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

177

479

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

479

SIp hold time

(from SCKp↑) Note 1

tKSI1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

Delay time from SCKp↓

to SOp output Note 1

tKSO1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

100

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

195

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k

483

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