R5F11BLE datasheet(73/143 Pages) RENESAS

73 / 143 page

RL78/G1F

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)

R01DS0246EJ0110 Rev. 1.10

Page 73 of 140

Aug 12, 2016

2.6.4

Comparator

Note 1.

Time taken until the comparator satisfies the DC/AC characteristics after the comparator operation enable signal is

switched (CMPnEN = 0 → 1).

Note 2.

Enable comparator output (CnOE bit = 1; n = 0 to 1) after enabling operation of the internal reference voltage generator

(by setting the CVREm bit to 1; m = 0 to 1) and waiting for the operation stabilization time to elapse.

2.6.5

PGA

Note 1.

Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA

operation has been enabled (PGAEN = 1).

(TA = -40 to +85°C, 2.7 V

≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input offset voltage

VIOCMP

±5

±40

Input voltage range

VICMP

0VDD

Internal reference

voltage deviation

∆VIREF

CmRVM register value : 7FH to 80H (m = 0, 1)

±2LSB

Other than above

±1LSB

Response Time

tCR, tCF

Input amplitude±100mV

150

Operation stabilization

timeNote 1

tCMP

CMPn = 0→1VDD = 3.3 to 5.5 V

μs

VDD = 2.7 to 3.3 V

μs

Reference voltage

stabilization wait time

tVR

CVRE : 0→1Note 2

μs

Operation current

ICMPDD

Separately, it is defined as the operation current of peripheral functions.

(TA = -40 to +85°C, 2.7 V

≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input offset voltage

VIOPGA

±10

Input voltage range

VIPGA

0.9

× VDD/

Gain

Output voltage range

VIOHPGA

0.93

× VDD

VIOLPGA

0.07

× VDD

Gain error

x4, x8

±1%

x16

±1.5

x32

±2%

Slew rate

SRRPGA Rising

When Vin= 0.1VDD/gain

to 0.9VDD/gain.

10 to 90% of output

voltage amplitude

4.0 V ≤ VDD ≤ 5.5 V

(Other than x32)

3.5

V/μs

4.0 V ≤ VDD ≤ 5.5 V (x32)

3.0

2.7 V ≤ VDD ≤ 4.0V

0.5

SRFPGA

Falling

When Vin= 0.1VDD/gain

to 0.9VDD/gain.

90 to 10% of output

voltage amplitude

4.0 V ≤ VDD ≤ 5.5 V

(Other than x32)

3.5

4.0 V ≤ VDD ≤ 5.5 V (x32)

3.0

2.7 V ≤ VDD ≤ 4.0V

0.5

Reference voltage

stabilization wait time-

Note 1

tPGA

x4, x8

μs

x16, x32

μs

Operation current

IPGADD

Separately, it is defined as the operation current of peripheral functions.

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