R5F10WMGG datasheet(39/126 Pages) RENESAS

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RL78/L13

2. ELECTRICAL SPECIFICATIONS (TA =

−40 to +85°C)

R01DS0168EJ0210 Rev.2.10

Aug 12, 2016

Page 39 of 123

Notes 1.

The value must also be equal to or less than fMCK/4.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Condition in the HS (high-speed main) mode

Caution

Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin

and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port

output mode register g (POMg).

Simplified I2C mode connection diagram (during communication at same potential)

RL78

microcontroller

SDAr

SCLr

SDA

SCL

User device

VDD

Simplified I2C mode serial transfer timing (during communication at same potential)

SDAr

tLOW

tHIGH

tHD : DAT

SCLr

tSU : DAT

1/fSCL

Remarks 1.

Rb[

Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load

capacitance

r: IIC number (r = 00, 10), g: PIM and POM number (g = 0, 1)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),

n: Channel number (n = 0-3), mn = 00-03, 10-13)

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R5F10WMGG Datasheet(PDF) 39 Page - Renesas Technology Corp