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R5F10WMGG Datasheet(PDF) 49 Page - Renesas Technology Corp |
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R5F10WMGG Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 126 page  RL78/L13 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0168EJ0210 Rev.2.10 Aug 12, 2016 Page 49 of 123 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle timeNote 1 tKCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 20 MHz < fMCK 12/fMCK – – ns 8 MHz < fMCK ≤ 20 MHz 10/fMCK – – ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK – ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 20 MHz < fMCK 16/fMCK – – ns 16 MHz < fMCK ≤ 20 MHz 14/fMCK – – ns 8 MHz < fMCK ≤ 16 MHz 12/fMCK – – ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/fMCK – ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3 20 MHz < fMCK 36/fMCK – – ns 16 MHz < fMCK ≤ 20 MHz 32/fMCK – – ns 8 MHz < fMCK ≤ 16 MHz 26/fMCK – – ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK 16/fMCK – ns fMCK ≤ 4 MHz 10/fMCK 10/fMCK 10/fMCK ns SCKp high- /low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 − 12 tKCY2/2 − 50 tKCY2/2 − 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 − 18 tKCY2/2 − 50 tKCY2/2 − 50 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3 tKCY2/2 − 50 tKCY2/2 − 50 tKCY2/2 − 50 ns SIp setup time (to SCKp ↑)Note 4 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns SIp hold time (from SCKp ↑)Note 5 tKSI2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns Delay time from SCKp ↓ to SOp outputNote 6 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 k Ω 2/fMCK + 120 2/fMCK + 573 2/fMCK + 573 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 k Ω 2/fMCK + 214 2/fMCK + 573 2/fMCK + 573 ns 1.8 V (2.4 VNote 2) ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 k Ω 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) |
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