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R5F564MFDDFB Datasheet(PDF) 153 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 153 Page - Renesas Technology Corp |
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153 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 153 of 228 Oct 24, 2016 RX64M Group 5. Electrical Characteristics 5.3.3 Timing of Recovery from Low Power Consumption Modes Note 1. The time for return after release from software standby is determined by the value obtained by adding the oscillation stabilization waiting time (tSBYOSCWTO) and the time required for operations by the software standby release sequencer (tSBYSEQ). Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization waiting time tSBYOSCWT is selected. Note 3. For n, the greatest value is selected from among the internal clock division settings. Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1. Table 5.18 Timing of Recovery from Low Power Consumption Modes (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions tSBYOSCWT*2 tSBYSEQ*3 Recovery time after cancellation of software standby mode*1 Crystal resonator connected to main clock oscillator Main clock oscillator operating tSBYMC — — {( MSTS[7:0] bits × 32 ) + 76 } / 0.216 100 μs + 7/f ICLK + 2n/fMAIN μs Figure 5.12 Main clock oscillator and PLL circuit operating tSBYPC {( MSTS[7:0] bits × 32 ) + 138 } / 0.216 100 μs + 7/f ICLK + 2n/fPLL External clock input to main clock oscillator Main clock oscillator operating tSBYEX 352 100 μs + 7/f ICLK + 2n/fEXMAIN Main clock oscillator and PLL circuit operating tSBYPE 639 100 μs + 7/f ICLK + 2n/fPLL Sub-clock oscillator operating tSBYSC {( SSTS[7:0] bits × 16384 ) + 13 } / 0.216 + 10/fFCLK 100 μs + 4/f ICLK + 2n/fSUB High-speed on-chip oscillator operating High-speed on-chip oscillator operating tSBYHO 454 100 μs + 7/f ICLK + 2n/fHOCO High-speed on-chip oscillator operating and PLL circuit operating tSBYPH 741 100 μs + 7/f ICLK + 2n/fPLL Low-speed on-chip oscillator operating*4 tSBYLO 338 100 μs + 7/f ICLK + 2n/fLOCO |
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