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R5F564MFDDFB Datasheet(PDF) 156 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 156 Page - Renesas Technology Corp |
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156 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 156 of 228 Oct 24, 2016 RX64M Group 5. Electrical Characteristics 5.3.4 Control Signal Timing Note 1. tPBcyc: PCLKB cycle Figure 5.14 NMI Interrupt Input Timing Figure 5.15 IRQ Interrupt Input Timing Table 5.20 Control Signal Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PLCKB = 8 to 60 MHz, Ta = Topr Item Symbol Min.*1 Typ. Max. Unit Test Conditions*1 NMI pulse width tNMIW 200 — — ns tPBcyc × 2 ≤ 200 ns, Figure 5.14 tPBcyc × 2 — — ns tPBcyc × 2 > 200 ns, Figure 5.14 IRQ pulse width tIRQW 200 — — ns tPBcyc × 2 ≤ 200 ns, Figure 5.15 tPBcyc × 2 — — ns tPBcyc × 2 > 200 ns, Figure 5.15 NMI tNMIW IRQ tIRQW |
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