PI7C7300 datasheet(7/109 Pages) PERICOM

7 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 7 OF 109

09/25/03 Revision 1.09

SUPPORTED COMMANDS ........................................................................................................ 69

13.1

PRIMARY INTERFACE ............................................................................................................. 69

13.2

SECONDARY INTERFACE....................................................................................................... 70

CONFIGURATION REGISTERS ............................................................................................... 70

14.1

CONFIGURATION REGISTER 1 AND 2 .................................................................................. 72

14.1.1

VENDOR ID REGISTER – OFFSET 00h............................................................................. 72

14.1.2

DEVICE ID REGISTER – OFFSET 00h .............................................................................. 73

14.1.3

COMMAND REGISTER – OFFSET 04h ............................................................................. 73

14.1.4

STATUS REGISTER – OFFSET 04h.................................................................................... 74

14.1.5

REVISION ID REGISTER – OFFSET 08h........................................................................... 75

14.1.6

CLASS CODE REGISTER – OFFEST 08h .......................................................................... 75

14.1.7

CACHE LINE SIZE REGISTER – OFFSET 0Ch ................................................................. 75

14.1.8

PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.................................................. 75

14.1.9

HEADER TYPE REGISTER – OFFSET 0Ch ....................................................................... 76

14.1.10

PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................... 76

14.1.11

SECONDARY (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h ............................ 76

14.1.12

SUBORDINATE (S1 or S2) BUS NUMBER REGISTER – OFFSET 18h ........................ 76

14.1.13

SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................ 76

14.1.14

I/O BASE REGISTER – OFFSET 1Ch ............................................................................. 77

14.1.15

I/O LIMIT REGISTER – OFFSET 1Ch ............................................................................ 77

14.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch........................................................ 77

14.1.17

MEMORY BASE REGISTER – OFFSET 20h................................................................... 78

14.1.18

MEMORY LIMIT REGISTER – OFFSET 20h.................................................................. 78

14.1.19

PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h .................................... 78

14.1.20

PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ................................... 79

14.1.21

PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET

28h

.......................................................................................................................................... 79

14.1.22

PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET

2Ch

.......................................................................................................................................... 79

14.1.23

I/O BASE ADDRESS UPPER 16-BITS REGISTER – Offset 30h..................................... 79

14.1.24

I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h............................... 80

14.1.25

ECP POINTER REGISTER – OFFSET 34h..................................................................... 80

14.1.26

BRIDGE CONTROL REGISTER – OFFSET 3Ch............................................................ 80

14.1.27

DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h ....................................... 81

14.1.28

ARBITER CONTROL REGISTER – OFFSET 40h........................................................... 83

14.1.29

UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h..................................... 83

14.1.30

HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch...................................... 83

14.1.31

UPSTREAM (S1 or S2 to P) MEMORY BASE REGISTER – OFFSET 50h..................... 84

14.1.32

UPSTREAM (S1 or S2 to P) MEMORY LIMIT REGISTER – OFFSET 50h.................... 84

14.1.33

UPSTREAM (S1 or S2 to P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET

54h

.......................................................................................................................................... 84

14.1.34

UPSTREAM (S1 or S2 to P) MEMORY LIMIT UPPER 32 BITS REGISTER – OFFSET

58h

.......................................................................................................................................... 85

14.1.35

P_SERR# EVENT DISABLE REGISTER – OFFSET 64h................................................ 85

14.1.36

SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ...................................... 86

14.1.37

PORT OPTION REGISTER – OFFSET 74h .................................................................... 86

14.1.38

MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h ......................................... 88

14.1.39

RETRY COUNTER REGISTER – OFFSET 78h............................................................... 88

14.1.40

SAMPLING TIMER REGISTER – OFFSET 7Ch............................................................. 88

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