PI7C7300 datasheet(80/109 Pages) PERICOM

80 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 80 OF 109

09/25/03 Revision 1.09

14.1.24

I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h

Bit

Function

Type

Description

31:0

I/O Limit

Address, Upper

16-bits [31:16]

R/W

Defines the upper 16-bits of a 32-bit top address of an address range

for the bridge to determine when to forward I/O transactions from

one interface to the other.

Reset to 0

14.1.25

ECP POINTER REGISTER – OFFSET 34h

Bit

Function

Type

Description

7:0

Enhanced

Capabilities Port

Pointer

R/O

Enhanced capabilities port offset pointer. Read as B0h to indicate

that the first item resides at that configuration offset.

14.1.26

BRIDGE CONTROL REGISTER – OFFSET 3Ch

Bit

Function

Type

Description

Parity Error

Response

R/W

Controls the bridge’s response to parity errors on the secondary

interface.

0: ignore address and data parity errors on the secondary interface

1: enable parity error reporting and detection on the secondary

interface

Reset to 0

S1_SERR#

enable

R/W

Controls the forwarding of S1_SERR# or S2_SERR# to the primary

interface.

0: disable the forwarding of S1_SERR# or S2_SERR# to primary

interface

1: enable the forwarding of S1_SERR# or S2_SERR# to primary

interface

Reset to 0

ISA enable

R/W

Modifies the bridge’s response to ISA I/O addresses, applying only to

those addresses falling within the I/O base and limit address registers

and within the first 64KB or PCI I/O space.

0: forward all I/O addresses in the range defined by the I/O base and

I/O limit registers

1: blocks forwarding of ISA I/O addresses in the range defined by the

I/O base and I/O limit registers that are in the first 64KB of I/O space

that address the last 768 bytes in each 1KB block. Secondary I/O

transactions are forwarded upstream if the address falls within the last

768 bytes in each 1KB block

Reset to 0

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