PI7C7300 datasheet(9/109 Pages) PERICOM

9 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 9 OF 109

09/25/03 Revision 1.09

TABLE 4-5 READ TRANSACTION PREFETCHING................................................................................ 28

TABLE 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING ....................................... 32

TABLE 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE.................................................. 37

TABLE 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION ............................................... 37

TABLE 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION ............................................. 38

TABLE 6-1 SUMMARY OF TRANSACTION ORDERING....................................................................... 48

TABLE 7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ....................... 56

TABLE 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ......................... 57

TABLE 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT.................... 57

TABLE 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT ............. 58

TABLE 7-5 ASSERTION OF P_PERR#....................................................................................................... 58

TABLE 7-6 ASSERTION OF S_PERR#....................................................................................................... 59

TABLE 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS................................................... 59

TABLE 16-1 TAP PINS ................................................................................................................................ 96

TABLE 16-2 JTAG BOUNDARY REGISTER ORDER .............................................................................. 98

LIST OF FIGURES

FIGURE 9-1 SECONDARY ARBITER EXAMPLE..................................................................................... 65

FIGURE 16-1 TEST ACCESS PORT BLOCK DIAGRAM.......................................................................... 95

FIGURE 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS ................................................. 102

FIGURE 18-1 272-PIN PBGA PACKAGE ................................................................................................. 104

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