AD9864-EBZ datasheet(36/48 Pages) AD

36 / 48 page

Data Sheet

AD9864

Rev. A | Page 35 of 47

–3

–6

NORMALIZED FREQUENCY OFFSET ((

fIN–fIF) fCLK)

–9

–18

0.03

0.04

0.05

0.02

0.01

–12

–15

Figure 61. Normalized RSSI Error vs. Normalized IF Frequency Offset

Automatic Gain Control (AGC)

The gain of the VGA (and DVGA) is automatically adjusted

when the AGC is enabled via the AGCR field of Register 0x06.

In this mode, the gain of the VGA is continuously updated at

fCLK/60 in an attempt to ensure that the maximum analog signal

level into the ADC does not exceed the ADC clip level and that

the rms output level of the ADC is equal to a programmable

reference level. With the DVGA enabled, the AGC control loop

also attempts to minimize the effects of 16-bit truncation noise

prior to the SSI output by continuously adjusting the gain of the

DVGA to ensure maximum digital gain while not exceeding the

programmable reference level.

This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB,

and 15 dB below the ADC saturation (clip) level by writing

values from 1 to 5 to the 3-bit AGCR field. Note that the ADC

clip level is defined to be 2 dB below its full scale (−18 dBm at

the LNA input for a matched input and maximum attenuation).

If AGCR is 0, automatic gain control is disabled. Because

clipping of the ADC input degrades the SNR performance, the

reference level must also take into consideration the peak-to-

rms characteristics of the target (or interferer) signals.

Referring again to Figure 59, the majority of the AGC loop

operates in the discrete time domain. The sample rate of the

loop is fCLK/60; therefore, registers associated with the AGC

algorithm are updated at this rate. The number of overload and

ADC reset occurrences within the final I/Q update rate of the

AD9864, as well as the AGC value (8 MSB), can be read from

the SSI data upon proper configuration.

The AGC performs digital signal estimation at the output of the

first decimation stage (DEC1) as well as the DVGA output that

follows the last decimation stage (DEC3). The rms power of the

I and Q signal is estimated by the equation

Xest[n] = Abs(I[n] + Abs(Q[n])

(7)

Signal estimation after the first decimation stage allows the

AGC to cope with out-of-band interferers and in-band signals

that could otherwise overload the ADC. Signal estimation after

the DVGA allows the AGC to minimize the effects of the 16-bit

truncation noise.

When the estimated signal level falls within the range of the

AGC, the AGC loop adjusts the VGA (or DVGA) attenuation

setting so that the estimated signal level is equal to the

programmed level specified in the AGCR field. The absolute

signal strength can be determined from the contents of the

ATTN and RSSI field that is available in the SSI data frame

when properly configured. Within this AGC tracking range, the

6-bit value in the RSSI field remains constant while the 8-bit

ATTN field varies according to the VGA/DVGA setting. Note

that the ATTN value is based on the 8 MSB contained in the

AGCG field of Register 0x03 and Register 0x04.

A description of the AGC control algorithm and the user

adjustable parameters follows. First, consider the case where the

in-band target signal is bigger than all out-of-band interferers

and the DVGA is disabled. With the DVGA disabled, a control

loop based only on the target signal power measured after

DEC1 is used to control the VGA gain, and the target signal is

tracked to the programmed reference level. If the signal is too

large, the attenuation is increased with a proportionality

constant determined by the AGCA setting. Large AGCA values

result in large gain changes, thus rapid tracking of changes in

signal strength. If the target signal is too small relative to the

reference level, the attenuation is reduced; however, now the

proportionality constant is determined by both the AGCA and

AGCD settings. The AGCD value is effectively subtracted from

AGCA, so a large AGCD results in smaller gain changes and

thus slower tracking of fading signals.

The 4-bit code in the AGCA field sets the raw bandwidth of the

AGC loop. With AGCA = 0, the AGC loop bandwidth is at its

minimum of 50 Hz, assuming fCLK = 18 MHz. Each increment of

AGCA increases the loop bandwidth by a factor of √2; thus the

maximum bandwidth is 9 kHz. A general expression for the

attack bandwidth is

BWA = 50 × (fCLK/18 MHz) × 2(AGCA/2) Hz

(8)

Assuming that the loop dynamics are essentially those of a

single-pole system, the corresponding attack time is

tATTACK = 2.2/(100 × π × 2(AGCA/2)) = 35/BWA

(9)

The 4-bit code in the AGCD field sets the ratio of the attack

time to the decay time in the amplitude estimation circuitry.

When AGCD is zero, this ratio is one. Incrementing AGCD

multiplies the decay time constant by 21/2, allowing a 180:1

range in the decay time relative to the attack time. The decay

time may be computed from

tDECAY = tATTACK × 2(AGCD/2)

(10)

Figure 62 shows the AGC response to a 30 Hz pulse-modulated

IF burst for different AGCA and AGCD settings. The 3-bit

value in the AGCO field determines the amount of attenuation

added in response to a reset event in the ADC. Each increment

in AGCO doubles the weighting factor. At the highest AGCO

setting, the attenuation changes from 0 dB to 12 dB in

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