AD9864-EBZ datasheet(26/48 Pages) AD

26 / 48 page

Data Sheet

AD9864

Rev. A | Page 25 of 47

Table 16. Standby Control Bits

STBY Bit

Effect

Current

Reduction

(mA)1

Wake-Up

Time (ms)

7: REF

Voltage reference off; all

biasing shut down.

0.6

<0.1

(CREF = 4.7 nF)

6: LO

LO synthesizer off,

IOUTL three-state.

1.2

See Note 2

5: CKO

Clock oscillator off.

1.1

See Note 2

4: CK

Clock synthesizer off,

IOUTC three-state. Clock

buffer off if ADC is off.

1.3

See Note 2

3: GC

Gain control DAC OFF.

GCP and GCN three-

state.

0.2

Depends on

CGC

2: LNAMX

LNA and mixer off.

CXVM, CXVL, and CXIF

three-state.

8.2

<2.2

1: Unused

0: ADC

ADC off; clock buffer off

if CLK synthesizer off;

VCM three-state; clock

to the digital filter

halted; digital outputs

static.

9.2

<0.1

When all blocks are in standby, the master reference circuit is also put into

standby, and thus the current is further reduced by 0.4 mA.

Wake-up time is dependent on programming and/or external components.

LO SYNTHESIZER

The LO synthesizer shown in Figure 39 is a fully programmable

phase-locked loop (PLL) capable of 6.25 kHz resolution at input

frequencies up to 300 MHz and reference clocks of up to 26 MHz.

It consists of a low noise, digital, phase-frequency detector (PFD),

a variable output current charge pump (CP), a 14-bit reference

divider, programmable A and B counters, and a dual-modulus

8/9 prescaler.

The A (3-bit) and B (13-bit) counters, in conjunction with the

dual 8/9 modulus prescaler, implement an N divider with N =

8 × B + A. In addition, the 14-bit reference counter (R counter)

allows selectable input reference frequencies, fREF, at the PFD

input. A complete PLL can be implemented if the synthesizer is

used with an external loop filter and voltage controlled

oscillator (VCO).

The A, B, and R counters can be programmed via the following

registers: LOA, LOB, and LOR. The charge pump output current

is programmable via the LOI register from 0.625 mA to 5.0 mA

using the equation

IPUMP = (LOI + 1) × 0.625 mA

(2)

An on-chip fast acquire function (enabled by the LOF bit)

automatically increases the output current for faster settling

during channel changes. The synthesizer can also be disabled

using the LO standby bit located in the STBY register.

fREF

fLO

FROM

VCO

REF

BUFFER

÷R

PHASE-

FREQUENCY

DETECTOR

FAST

ACQUIRE

CHARGE

PUMP

TO EXTERNAL

LOOP

FILTER

BUFFER

8/9

A. B

COUNTERS

LOR

LOA, LOB

Figure 39. LO Synthesizer

The LO (and CLK) synthesizer works in the following manner.

The externally supplied reference frequency, fREF, is buffered and

divided by the value held in the R counter. The internal fREF is

then compared to a divided version of the VCO frequency, fLO.

The phase/frequency detector provides up and down pulses

whose widths vary, depending upon the difference in phase and

frequency of the input signals of the detector. The up/down

pulses control the charge pump, making current available to

charge the external low-pass loop filter when there is a

discrepancy between the inputs of the PFD. The output of the

low-pass filter feeds an external VCO whose output frequency,

fLO, is driven such that its divided down version, fLO, matches

that of fREF, thus closing the feedback loop.

The synthesized frequency is related to the reference frequency

and the LO register contents as follows:

fLO = (8 × LOB + LOA)/LOR × fREF

(3)

Note that the minimum allowable value in the LOB register is 3,

and its value must always be greater than that loaded into LOA.

An example helps to illustrate how the values of LOA, LOB, and

LOR can be selected. Consider an application employing a

13 MHz crystal oscillator (fREF = 13 MHz), with the requirement

that fREF = 100 kHz and fLO = 143 MHz, that is, high side injection

with fIF = 140.75 MHz and fCLK = 18 MSPS. LOR is selected to be

130 so that fREF = 100 kHz. The N-divider factor is 1430, which

can be realized by selecting LOB = 178 and LOA = 6.

The stability, phase noise, spur performance, and transient

response of the AD9864 LO (and CLK) synthesizers are

determined by the external loop filter, the VCO, the N-divide

factor, and the reference frequency, fREF. A good overview of the

theory and practical implementation of PLL synthesizers

(featured as a 3-part series in Analog Dialogue) can be found on

the Analog Devices website. A free software copy of the Analog

Devices ADIsimPLL, a PLL synthesizer simulation tool, is also

available at www.analog.com. Note that the ADF4112 can be

used as a close approximation to the LO synthesizer of the

AD9864 when using this software tool.

AD9864-EBZ Datasheet(PDF) 26 Page - Analog Devices

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