AD9864-EBZ datasheet(23/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 22 of 47

CLKOUT

DOUT

CLKOUT

DOUT

CLKOUT

DOUT

CLKOUT

DOUT

I15

Q15

Q14

I15

Q15

Q14

I15

Q15

Q14

ATTN7

ATTEN6

RSSI0

I15

Q15

STOP

BIT

START

BIT

STOP

BIT

START

BIT

SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0

SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0

SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC

SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0

SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0; AS ABOVE, BUT FS IS LOW

IDLE (HIGH) BITS

HI-Z

Figure 33. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data

Table 14. Number of Bits per Frame for Different SSICR

Settings

EAGC

EFS

AAGC

Number of Bits per Frame

0 (16 Bits)

N/A

491

691

591

1 (24 Bits)

N/A

691

891

791

The number of bits per frame with embedded frame sync (EFS = 1); assume

at least 10 idle bits are desired.

N/A means not applicable.

The maximum SSIORD setting can be determined by the

following equation:

SSIORD < TRUNC[(Decimation Factor)/(Number of

Bits per Frame)]

(1)

where TRUNC is the truncated integer value.

If SSIORD = (decimation factor)/(number of bits per frame),

the last bit in the SSI frame is not clocked out prior to FS

returning high.

Table 14 lists the number of bits within a frame for 16-bit and 24-bit

output data formats for all of the different SSICR settings. The

decimation factor is determined by the contents of Register 0x07.

An example helps illustrate how the maximum SSIORD setting

is determined. Suppose a user selects a decimation factor of 600

(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with a

dedicated frame sync (EFS = 0) containing 24-bit data (DW = 1)

with nonalternating embedded AGC data included (EAGC = 1,

AAGC = 0). Referring to Table 14, each frame consists of 64

data bits. Using Equation 1, the maximum SSIORD setting is

9 (= TRUNC(600/64)). Therefore, the user can select any

SSIORD setting between 1 and 9.

Figure 33 illustrates the output timing of the SSI port for several

SSI control register settings with 16-bit I/Q data, and Figure 34

shows the associated timing parameters. Note that the same

timing relationship holds for 24-bit I/Q data, with the exception

that I and Q word lengths now become 24 bits. In the default mode

of operation, data is shifted out on rising edges of CLKOUT

after a pulse equal to a clock period is output from the frame

sync (FS) pin. As described above, the output data consists of a

16-bit or 24-bit I sample followed by a 16-bit or 24-bit Q sample,

plus two optional bytes containing AGC and status information.

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