AD9864-EBZ datasheet(28/48 Pages) AD

28 / 48 page

Data Sheet

AD9864

Rev. A | Page 27 of 47

VDDC = 3.0V

IOUTC

LOSC

0.1µF

RBIAS

LOOP

FILTER

AD9864

CLKN

CLKP

RF CP

CVAR

COSC

VCM = VDDC – RBIAS × IBIAS > 1.6V

fOSC > 1/{2 × (LOSC × (CVARACTOR||COSC))1/2}

CLK OSC. BIAS

IBIAS = 0.15mA, 0.25mA,

0.40mA, OR 0.65mA

Figure 41. External Loop Filter, Varactor, and LC Tank Required to Realize a

Complete Clock Synthesizer

The AD9864 clock synthesizer circuitry includes a negative

resistance core so that only an external LC tank circuit with a

varactor is needed to realize a voltage controlled clock oscillator

(VCO). Figure 41 shows the external components required to

complete the clock synthesizer along with the equivalent input

circuitry of the CLK input. The resonant frequency of the VCO

is approximately determined by LOSC and the series equivalent

capacitance of COSC and CVAR. As a result, LOSC, COSC, and CVAR

must be selected to provide a sufficient tuning range to ensure

both proper start-up oscillation and locking of the clock

synthesizer. Both the COSC and LOSC values must have ±5%

tolerance along with LOSC having a Q > 20 at the desired clock

frequency.

The bias, IBIAS, of the negative-resistance core has four

programmable settings. The lower equivalent Q of the LC tank

circuit may require a higher bias setting of the negative

resistance core to ensure proper oscillation. Select RBIAS so that the

common-mode voltage at CLKP and CLKN is approximately 1.6 V.

The synthesizer may be disabled via the CK standby bit to allow the

user to employ an external synthesizer and/or VCO in place of

those resident on the IC. Note that if an external CLK source or

VCO is used, the clock oscillator must be disabled via the CKO

standby bit.

The phase noise performance of the clock synthesizer is

dependent on several factors, including the CLK oscillator IBIAS

setting, charge pump setting, loop filter component values, and

internal fREF setting. Figure 42 and Figure 43 show how the

measured phase noise attributed to the clock synthesizer varies

(relative to an external fCLK) as a function of the IBIAS setting and

charge pump setting for a −31 dBm IFIN signal at 73.35 MHz

with an external LO signal at 71.1 MHz. Figure 42 shows that

the optimum phase noise is achieved with the highest IBIAS

(CKO) setting, while Figure 43 shows that the higher charge

pump values provide the optimum performance for the given

loop filter configuration. The AD9864 clock synthesizer and

oscillator were set up to provide an fCLK of 18 MHz from an

external fREF of 16.8 MHz. The following external component

values were selected for the synthesizer: RF = 390 Ω, RD = 2 kΩ,

CZ = 0.68 μF, CP = 0.1 μF, COSC = 91 pF, LOSC = 1.2 μH, and

CVAR = Toshiba 1SV228 varactor.

–25

–90

–100

–110

–120

–20

–15

–10

–5

FREQUENCY OFFSET (kHz)

–80

–70

–60

–50

–40

–30

–20

–10

–130

–140

CKO = 1

CK0 = 0

CKO = 2

CKO = 3

EXT CLK

Figure 42. CLK Phase Noise vs. IBIAS Setting (CKO);

IF = 73.35 MHz, IF = 71.1 MHz, IFIN = −31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz;

CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with fREF = 300 kHz

–25

–90

–100

–110

–120

–20

–15

–10

FREQUENCY OFFSET (kHz)

–80

–70

–60

–50

–40

–30

–20

–10

–130

–140

CP = 0

CP = 2

CP = 4

CP = 6

EXT CLK

Figure 43. CLK Phase Noise vs. IBIAS Setting (CKO);

IF = 73.35 MHz, IF = 71.1 MHz, IFIN = −31 dBm, fCLK = 18 MHz, fREF = 16.8 MHz;

CLK SYN Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with fREF = 300 kHz

Table 18. SPI Registers Associated with CLK Synthesizer

Address (Hex)

Bit(s)

Width

Default Value

Name

0x00

[7:0]

0xFF

STBY

0x01

[3:2]

0x00

CKOB

0x10

[5:0]

0x00

CKR [13:8]

0x11

[7:0]

0x38

CKR [7:0]

0x12

[4:0]

0x00

CKN [12:8]

0x13

[7:0]

0x3C

CKN [7:0]

0x14

CKF

CKINV

[4:2]

0x00

CKI

[1:0]

0x00

CKTM

0x15

[3:0]

0x00

CKFA [13:8]

0x16

[7:0]

0x04

CKFA [7:0]

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