AR0230CS datasheet(15/24 Pages) ONSEMI

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AR0230CS

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Table 5.

TWO−WIRE SERIAL BUS CHARACTERISTICS

(fEXTCLK = 27 MHz;VDD = 1.8V; VDD_ IO = 2.8V;VAA_PIX = 2.8V;VDD_ PLL = 2.8V; TA = 25°C)

Parameter

Symbol

Standard Mode

Fast Mode

Unit

SCLK Clock Frequency

fSCL

100

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

tHD;STA

4.0

−

0.6

−

μs

LOW period of the SCLK clock

tLOW

4.7

−

1.3

−

μs

HIGH period of the SCLK clock

tHIGH

4.0

−

0.6

−

μs

Set−up time for a repeated START con-

dition

tSU;STA

4.7

−

0.6

−

μs

Data hold time

tHD;DAT

3.455

0.95

μs

Data set−up time

tSU;DAT

250

−

1006

−

Rise time of both SDATA and SCLK sig-

nals

−

1000

20 + 0.1Cb7

300

Fall time of both SDATA and SCLK signals

−

300

20 + 0.1Cb7

300

Set−up time for STOP condition

tSU;STO

4.0

−

0.6

−

μs

Bus free time between a STOP and

START condition

tBUF

4.7

−

1.3

−

μs

Capacitive load for each bus line

−

400

−

400

Serial interface input pin capacitance

CIN_SI

−

3.3

−

3.3

SDATA max load capacitance

CLOAD_SD

−

SDATA pull−up resistor

RSD

1.5

4.7

1.5

4.7

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two−wire control is I2C−compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

6. A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW

period of the SCLK signal, it must output the next data bit to the SDATA linet r max + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard−mode I2C−bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

I/O Timing

By default, the AR0230CS launches pixel data, FV, and

LV with the falling edge of PIXCLK. The expectation is that

the user captures DOUT[11:0], FV, and LV using the rising

edge of PIXCLK.

See Figure 10 below and Table 6 for I/O timing (AC)

characteristics.

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