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TMS320VC5471GHKA Datasheet(PDF) 37 Page - Texas Instruments |
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TMS320VC5471GHKA Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 97 page ![]() DSP Subsystem Functional Overview 28 June 2001 – Revised December 2002 SPRS180C The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 3–7. The function of each bit is described in Table 3–13. 15 14 13 12 11 10 9 8 Reserved DMAC5 DMAC4 BXINT1/ DMAC3 BRINT1/ DMAC2 AINT Reserved 7 65 43 21 0 DMAC1 DMAC0 BXINT0 BRINT0 TINT Reserved INT0 Figure 3–7. IFR and IMR Registers Table 3–13. IFR and IMR Register Bit Fields BIT FUNCTION NUMBER NAME FUNCTION 15–14 – Reserved 13 DMAC5 DMA channel 5 interrupt flag/mask bit 12 DMAC4 DMA channel 4 interrupt flag/mask bit 11 BXINT1/DMAC3 McBSP1 transmit interrupt flag/mask bit 10 BRINT1/DMAC2 McBSP1 receive interrupt flag/mask bit 9 AINT ARM-to-DSP interrupt flag/mask 8 – Reserved 7 DMAC1 DMA channel 1 interrupt flag/mask bit 6 DMAC0 DMA channel 0 interrupt flag/mask bit 5 BXINT0 McBSP0 transmit interrupt flag/mask bit 4 BRINT0 McBSP0 receive interrupt flag/mask bit 3 TINT Timer interrupt flag/mask bit 2–1 – Reserved 0 INT0 External interrupt 0 flag/mask bit |
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