TMS320VC5471GHKA datasheet(61/97 Pages) TI

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Electrical Specifications

June 2001 – Revised December 2002

SPRS180C

6.6

Memory and Parallel I/O Interface Timing

6.6.1 Memory Read

Table 6–6 and Table 6–7 assume testing over recommended operating conditions with DSP_MSTRB = 0 and

H = 0.5tc(CO) (see Figure 6–4).

Table 6–6. Memory Read Timing Requirements†

MIN

MAX

UNIT

ta(A)M

Access time, read data access from address valid

2H–15‡

ta(MSTRBL)

Access time, read data access from DSP_MSTRB low

2H–15‡

tsu(D)R

Setup time, read data before DSP_CLKOUT low

th(D)R

Hold time, read data after DSP_CLKOUT low

th(A-D)R

Hold time, read data after address invalid

th(D)MSTRBH Hold time, read data after DSP_MSTRB high

† Address, DSP_PS, and DSP_DS timings are all included in timings referenced as address.

‡ This access timing reflects a zero wait-state timing.

Table 6–7. Memory Read Switching Characteristics†

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, DSP_CLKOUT low to address valid§

1.5

11.5

td(CLKH-A)

Delay time, DSP_CLKOUT high (transition) to address valid¶

1.5

11.5

td(CLKL-MSL)

Delay time, DSP_CLKOUT low to DSP_MSTRB low

1.5

11.5

td(CLKL-MSH)

Delay time, DSP_CLKOUT low to DSP_MSTRB high

1.5

11.5

th(CLKL-A)R

Hold time, address valid after DSP_CLKOUT low§

1.5

11.5

th(CLKH-A)R

Hold time, address valid after DSP_CLKOUT high¶

1.5

11.5

† Address, DSP_PS, and DSP_DS timings are all included in timings referenced as address.

§ In the case of a memory read preceded by a memory read

¶ In the case of a memory read preceded by a memory write

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