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CS8952 Datasheet(PDF) 9 Page - Cirrus Logic |
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CS8952 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 82 page  CS8952 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 9 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES Parameter Symbol Min Typ Max Unit RX_CLK Period tP -40 - ns RX_CLK Pulse Width tWL, tWH -20 - ns RXD[3:0],RX_ER/RXD4,RX_DV setup to rising edge of RX_CLK tSU 10 - - ns RXD[3:0],RX_ER/RXD4,RX_DV hold from rising edge of RX_CLK tHD 10 - - ns CRStoRXD latency 4BAligned 5B Aligned tDLAT 2 2 3- 6 3- 6 8 8 BT “Start of Stream” to CRS asserted tCRS1 -10 11 BT “End of Stream” to CRS de-asserted tCRS2 -- 21 BT “Start of Stream” to COL asserted tCOL1 -- 11 BT “End of Stream” to COL de-asserted tCOL2 -- 21 BT RX_EN asserted to RX_DV, RXD[3:0] valid tEN -TBD - ns RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER/RXD4 in high impedance state tDIS -TBD - ns RX_CLK RXD[3:0], CRS tCRS1 tCOL2 tRLAT Start of Stream End of Stream RX_EN RX+/- RX_DV IN OUT IN OUT OUT OUT OUT COL tCOL1 tCRS2 tHD tEN tDIS RX_ER/RXD4 tWL tWH tP tSU |
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