CS8952 datasheet(3/82 Pages) CIRRUS

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CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

10BASE-T Serial Application ....................................................................... 25

Auto-Negotiation ................................................................................................. 25

Reset Operation .................................................................................................. 26

LED Indicators..................................................................................................... 26

MEDIA INDEPENDENT INTERFACE (MII) ................................................................. 27

MII Frame Structure ............................................................................................ 27

MII Receive Data................................................................................................. 28

MII Transmit Data................................................................................................ 28

MII Management Interface .................................................................................. 29

MII Management Frame Structure ...................................................................... 29

CONFIGURATION ...................................................................................................... 30

Configuration At Power-up/Reset Time............................................................... 30

Configuration Via Control Pins ............................................................................ 30

Configuration via the MII ..................................................................................... 30

CS8952 REGISTERS .................................................................................................. 31

Basic Mode Control Register - Address 00h ..................................................... 32

Basic Mode Status Register - Address 01h ...................................................... 34

PHY Identifier, Part 1 - Address 02h ................................................................. 36

PHY Identifier, Part 2 - Address 03h ................................................................. 37

Auto-Negotiation Advertisement Register - Address 04h .................................. 38

Auto-Negotiation Link Partner Ability Register - Address 05h ........................... 39

Auto-Negotiation Expansion Register - Address 06h ........................................ 40

Auto-Negotiation Next-Page Transmit Register - Address 07h ......................... 41

Interrupt Mask Register - Address 10h ............................................................. 42

Interrupt Status Register - Address 11h ............................................................ 45

Disconnect Count Register - Address 12h ........................................................ 48

False Carrier Count Register - Address 13h ..................................................... 49

Scrambler Key Initialization Register - Address 14h ......................................... 50

Receive Error Count Register - Address 15h .................................................... 51

Descrambler Key Initialization Register - Address 16h ..................................... 52

PCS Sub-Layer Configuration Register - Address 17h ..................................... 53

Loopback, Bypass, and Receiver Error Mask Register - Address 18h ............. 56

Self Status Register - Address 19h ................................................................... 59

10BASE-T Status Register - Address 1Bh ........................................................ 61

10BASE-T Configuration Register - Address 1Ch ............................................ 62

DESIGN CONSIDERATIONS ...................................................................................... 64

Twisted Pair Interface ......................................................................................... 64

100BASE-FX Interface........................................................................................ 64

Internal Voltage Reference ................................................................................. 64

Clocking Schemes .............................................................................................. 65

Recommended Magnetics .................................................................................. 66

Power Supply and Decoupling ............................................................................ 66

General Layout Recommendations..................................................................... 66

PIN DESCRIPTIONS ................................................................................................... 69

PACKAGE DIMENSIONS ........................................................................................... 81

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