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HT67F5652 Datasheet(PDF) 65 Page - Holtek Semiconductor Inc |
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HT67F5652 Datasheet(HTML) 65 Page - Holtek Semiconductor Inc |
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65 / 224 page ![]() Rev. 1.00 �4 De�e��e� 0�� �01� Rev. 1.00 �5 De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU WatchdogTimerEnable/DisableControlUndernormalprogramoperation,aWatchdogTimertime- outwillinitialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEP orIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbe setandonlytheProgramCounterandStackPointerwillbereset.Threemethodscanbeadopted toclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalue except01010Band10101BwrittenintotheWE4~WE0bitfiled,thesecondisusingtheWatchdog TimersoftwareclearinstructionsandthethirdisviaaHALTinstruction. ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse thesingle"CLRWDT"instructiontocleartheWDT. Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8 secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration. “CLR WDT” Inst�u�tion WE4~WE0 �its WDTC Registe� Reset MCU fS CLR “HALT” Inst�u�tion fSUB M U X Configu�ation option M U X fSYS/4 LXT LIRC Configu�ation option 8-stage Divide� WDT P�es�ale� fS/�8 8-to-1 MUX WS�~WS0 WDT Ti�e-out Watchdog Timer |
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