MB9B320M datasheet(3/108 Pages) CYPRESS

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Document Number: 002-05652 Rev. *D

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MB9B320M Series

Quadrature Position/Revolution Counter (QPRC)

(Max two channels)

The Quadrature Position/Revolution Counter (QPRC) is used

to measure the position of the position encoder. Moreover, it is

possible to use as the up/down counter.

The detection edge of the three external event input pins AIN,

BIN and ZIN is configurable.

16-bit position counter

16-bit revolution counter

Two 16-bit compare registers

Multi-function Timer

The Multi-function timer is composed of the following blocks.

16-bit free-run timer × 3ch./unit

Input capture × 4ch./unit

Output compare × 6ch./unit

A/D activation compare × 2ch./unit

Waveform generator × 3ch./unit

16-bit PPG timer × 3ch./unit

The following function can be used to achieve the motor

control.

PWM signal output function

DC chopper waveform output function

Dead time function

Input capture function

A/D convertor activate function

DTIF (Motor emergency stop) interrupt function

Real-time clock (RTC)

The Real-time clock can count

Year/Month/Day/Hour/Minute/Second/A day of the week from

00 to 99.

The interrupt function with specifying date and time

(Year/Month/Day/Hour/Minute) is available. This function is

also available by specifying only Year, Month, Day, Hour or

Minute.

Timer interrupt function after set time or each set time.

Capable of rewriting the time with continuing the time count.

Leap year automatic count is available.

Watch Counter

The Watch counter is used for wake up from Sleep and Timer

mode.

Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz

External Interrupt Controller Unit

Up to 23 external interrupt input pins @ 80 pin Package

Include one non-maskable interrupt (NMI) input pin

Watchdog Timer (Two channels)

A watchdog timer can generate interrupts or a reset when a

time-out value is reached.

This series consists of two different watchdogs, a "Hardware"

watchdog and a "Software" watchdog.

The "Hardware" watchdog timer is clocked by the built-in

Low-speed CR oscillator. Therefore, the "Hardware" watchdog

is active in any low-power consumption modes except RTC,

Stop, Deep Standby RTC, Deep Standby Stop modes.

CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator calculates the CRC which has a heavy

software processing load, and achieves a reduction of the

integrity check processing load for reception data and storage.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

CCITT CRC16 Generator Polynomial: 0x1021

IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

Clock and Reset

[Clocks]

Selectable from five clock sources (2 external oscillators, 2

built-in CR oscillators, and Main PLL).

Main Clock:

4 MHz to 48 MHz

Sub Clock:

32.768 kHz

Built-in High-speed CR Clock: 4 MHz

Built-in Low-speed CR Clock: 100 kHz

Main PLL Clock

[Resets]

Reset requests from INITX pin

Power-on reset

Software reset

Watchdog timers reset

Low-voltage detection reset

Clock Super Visor reset

Clock Super Visor (CSV)

Clocks generated by built-in CR oscillators are used to

supervise abnormality of the external clocks.

If external clock failure (clock stop) is detected, reset is

asserted.

If external frequency anomaly is detected, interrupt or reset is

asserted.

MB9B320M Datasheet(PDF) 3 Page - Cypress Semiconductor

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