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MB9B360L Datasheet(PDF) 76 Page - Cypress Semiconductor |
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MB9B360L Datasheet(HTML) 76 Page - Cypress Semiconductor |
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76 / 128 page  Document Number: 002-04930 Rev.*B Page 76 of 128 MB9B360L Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. |
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