MB9B360L datasheet(90/128 Pages) CYPRESS

90 / 128 page

Document Number: 002-04930 Rev.*B

Page 90 of 128

MB9B360L Series

When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Conditions

VCC < 4.5 V

VCC

≥ 4.5 V

Unit

Min

Max

Min

Max

SCS↓→SCK↑setup time

tCSSI

Internal shift

clock

operation

(*1)-20

(*1)+0

(*1)-20

(*1)+0

SCK↓→SCS↑ hold time

tCSHI

(*2)+0

(*2)+20

(*2)+0

(*2)+20

SCS deselect time

tCSDI

(*3)-20+5tCYCP

(*3)+20+5tCYCP

(*3)-20+5tCYCP

(*3)+20+5tCYCP

SCS↓→SCK↑setup time

tCSSE

External shift

clock

operation

3tCYCP+15

SCK↓→SCS↑ hold time

tCSHE

SCS deselect time

tCSDE

3tCYCP+15

SCS↓→SOT delay time

tDSE

SCS↑→SOT delay time

tDEE

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

tCYCP indicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part

(002-04856).

−

When the external load capacitance CL = 30 pF.

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