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MB9B360L Datasheet(PDF) 1 Page - Cypress Semiconductor |
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MB9B360L Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 128 page  MB9B360L Series 32-Bit Arm ® Cortex®-M4F FM4 Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-04930 Rev.*B Revised December 15, 2017 Devices in the MB9B360L Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the Arm ® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I 2C, LIN). The products that are described in this datasheet are placed into TYPE2-M4 product categories in the "FM4 Family Peripheral Manual Main Part (002-04856)”. Features 32-bit Arm ® Cortex®-M4F Core Processor version: r0p1 Up to 160 MHz Frequency Operation FPU built-in Support DSP instruction Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-Chip Memories [Flash Memory] These series are based on two independent on-chip Flash memories. MainFlash memory Up to 512 Kbytes Built-in Flash Accelerator System with 16 Kbytes trace buffer memory The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. Security function for code protection WorkFlash memory 32 Kbytes Read cycle: • 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0wait-cycle: the operation frequency up to 40 MHz Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. SRAM0: Up to 32 Kbytes SRAM1: Up to 16 Kbytes SRAM2: Up to 16 Kbytes USB Interface USB interface is composed of Device and Host. USB device USB2.0 Full-Speed supported Max 6 Endpoint supported • Endpoint 0 is control transfer • Endpoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer • Endpoint 3 to 5 can select Bulk-transfer or Interrupt-transfer • Endpoint 1 to 5 comprise Double Buffer The size of each endpoint is according to the follows. • Endpoint 0, 2 to 5: 64 bytes • Endpoint 1: 256 bytes USB host USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support USB Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet-length supported Wake-up function supported |
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