ADS112C04IPWR datasheet(39/72 Pages) TI1

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SLAVE ADDRESS

WREG

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SLAVE ADDRESS

RREG

SLAVE ADDRESS

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SLAVE ADDRESS

RDATA

SLAVE ADDRESS

CONVERSION DATA (MSB)

CONVERSION DATA (LSB)

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ADS112C04

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8.5.3.5 RDATA (0001 xxxx)

The RDATA command loads the output shift register with the most recent conversion result. Reading conversion

data must be performed as shown in Figure 57 by using two I2C communication frames. The first frame is an I2C

write operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host

sends the RDATA command to the ADS112C04. The second frame is an I2C read operation where the R/W bit

at the end of the address byte is 1 to indicate a read. The ADS112C04 reports the latest ADC conversion data in

this second I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY

pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,

DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is

high.

Figure 57. Read Conversion Data Sequence

8.5.3.6 RREG (0010 rrxx)

The RREG command reads the value of the register at address rr. Reading a register must be performed as

shown in Figure 58 by using two I2C communication frames. The first frame is an I2C write operation where the

R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RREG command

including the register address to the ADS112C04. The second frame is an I2C read operation where the R/W bit

at the end of the address byte is 1 to indicate a read. The ADS112C04 reports the contents of the requested

Figure 58. Read Register Sequence

8.5.3.7 WREG (0100 rrxx dddd dddd)

The WREG command writes dddd dddd to the register at address rr. Multiple registers can be written within the

same I2C frame by simply issuing another WREG command without providing a STOP condition following the

previous register write. Figure 59 shows the sequence for writing an arbitrary number of registers. The R/W bit at

the end of the address byte is 0 to indicate a write. The WREG command forces the digital filter to reset and any

ongoing ADC conversion to restart.

Figure 59. Write Register Sequence

8.5.4 Reading Data and Monitoring for New Conversion Results

Conversion data are read by issuing the RDATA command. The ADS112C04 responds to the RDATA command

with the latest conversion result. There are three ways to monitor for new conversion data.

One way is to monitor for the falling edge of the DRDY signal. When DRDY falls low, a new conversion result is

available for retrieval using the RDATA command. Figure 60 illustrates the timing diagram for collecting data

using the DRDY signal to indicate new data.

ADS112C04IPWR Datasheet(PDF) 39 Page - Texas Instruments

ADS112C04IPWR Datasheet(HTML) 39 Page - Texas Instruments

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