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ADS112C04IPWR Datasheet(PDF) 4 Page - Texas Instruments

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Part # ADS112C04IPWR
Description  16-Bit, 4-Channel, 2-kSPS, Delta-Sigma ADC With I2C Interface
PDF  72 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS112C04IPWR Datasheet(HTML) 4 Page - Texas Instruments

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ADS112C04
SBAS894 – APRIL 2018
www.ti.com
Product Folder Links: ADS112C04
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
(1)
MIN
MAX
UNIT
Power-supply voltage
AVDD to AVSS
–0.3
7
V
DVDD to DGND
–0.3
7
AVSS to DGND
–2.8
0.3
Analog input voltage
AIN0, AIN1, AIN2, AIN3, REFP, REFN
AVSS – 0.3
AVDD + 0.3
V
Digital input voltage
SCL, SDA, A0, A1, DRDY, RESET
DGND – 0.3
7
V
Input current
Continuous, any pin except power-supply pins
–10
10
mA
Temperature
Junction, TJ
150
°C
Storage, Tstg
–60
150
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±750
(1)
AINP and AINN denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs.
PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Low-Noise Programmable Gain Stage section for more information.
(2)
VINMAX denotes the maximum differential input voltage, VIN, that is expected in the application. |VINMAX| can be smaller than VREF / Gain.
(3)
Excluding the effects of offset and gain error.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Unipolar analog power supply
AVDD to AVSS
2.3
5.5
V
AVSS to DGND
–0.1
0
0.1
Bipolar analog power supply
AVDD to DGND
2.3
2.5
2.75
V
AVSS to DGND
–2.75
–2.5
–2.3
Digital power supply
DVDD to DGND
2.3
5.5
V
ANALOG INPUTS(1)
V(AINx)
Absolute input voltage(2)
PGA disabled, gain = 1 to 4
AVSS – 0.1
AVDD + 0.1
V
PGA enabled, gain = 1 to 4
AVSS + 0.2
AVDD – 0.2
PGA enabled, gain = 8 to 128
AVSS + 0.2 +
|VINMAX|·(Gain – 4) / 8
AVDD – 0.2 –
|VINMAX|·(Gain – 4) / 8
VIN
Differential input voltage
VIN = VAINP – VAINN
(3)
–VREF / Gain
VREF / Gain
V
VOLTAGE REFERENCE INPUTS
VREF
Differential reference input voltage
VREF = V(REFP) – V(REFN)
0.75
2.5
AVDD – AVSS
V
V(REFN)
Absolute negative reference voltage
AVSS – 0.1
V(REFP) – 0.75
V
V(REFP)
Absolute positive reference voltage
V(REFN) + 0.75
AVDD + 0.1
V
DIGITAL INPUTS
Input voltage
SCL, SDA, A0, A1, DRDY,
2.3 V
≤ DVDD < 3.0 V
DGND
DVDD + 0.5
V
SCL, SDA, A0, A1, DRDY,
3.0 V
≤ DVDD ≤ 5.5 V
DGND
5.5
RESET
DGND
DVDD
TEMPERATURE RANGE
TA
Operating ambient temperature
–40
125
°C



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