 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS112C04IPWR Datasheet(PDF) 8 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS112C04IPWR Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 72 page  8 ADS112C04 SBAS894 – APRIL 2018 www.ti.com Product Folder Links: ADS112C04 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 6.6 I 2C Timing Requirements over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor = 1 kΩ (unless otherwise noted) MIN MAX UNIT STANDARD-MODE fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 4 µs tLOW Pulse duration, SCL low 4.7 µs tHIGH Pulse duration, SCL high 4.0 µs tSU;STA Setup time, repeated START condition 4.7 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 250 ns tr Rise time, SCL, SDA 1000 ns tf Fall time, SCL, SDA 250 ns tSU;STO Setup time, STOP condition 4.0 µs tBUF Bus free time, between STOP and START condition 4.7 µs tVD;DAT Valid time, data 3.45 µs tVD;ACK Valid time, acknowledge 3.45 µs FAST-MODE fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs tLOW Pulse duration, SCL low 1.3 µs tHIGH Pulse duration, SCL high 0.6 µs tSU;STA Setup time, repeated START condition 0.6 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 100 ns tr Rise time, SCL, SDA 20 300 ns tf Fall time, SCL, SDA 20 · (DVDD / 5.5 V) 250 ns tSU;STO Setup time, STOP condition 0.6 µs tBUF Bus free time, between STOP and START condition 1.3 µs tVD;DAT Valid time, data 0.9 µs tVD;ACK Valid time, acknowledge 0.9 µs tSP Pulse width of spikes that must be suppressed by the input filter 0 50 ns FAST-MODE PLUS fSCL SCL clock frequency 0 1000 kHz tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 0.26 µs tLOW Pulse duration, SCL low 0.5 µs tHIGH Pulse duration, SCL high 0.26 µs tSU;STA Setup time, repeated START condition 0.26 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 50 ns tr Rise time, SCL, SDA 120 ns tf Fall time, SCL, SDA Pullup resistor = 350 Ω 20 · (DVDD / 5.5 V) 120 ns tSU;STO Setup time, STOP condition 0.26 µs tBUF Bus free time, between STOP and START condition 0.5 µs tVD;DAT Valid time, data 0.45 µs tVD;ACK Valid time, acknowledge 0.45 µs tSP Pulse duration of spikes that must be suppressed by the input filter 0 50 ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
