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AS3956 Datasheet(PDF) 67 Page - ams AG |
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AS3956 Datasheet(HTML) 67 Page - ams AG |
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67 / 109 page ![]() ams Datasheet Page 67 [v1-10] 2018-Apr-27 Document Feedback AS3956 − Detailed Description SPI Timing Figure 65: SPI Timing Note(s): 1. TSCLK=TSCLKL+TSCLKH, during EEPROM read the SCLK period has to be increased to 1μs (this limitation is imposed by EEPROM read access time) 2. TNCSL = 300μs min in Power mode 0. Symbol Parameter Min Typ Max Unit Note General Timing (VP_IO= 3.3V, Temperature 25°C) TSCLK SCLK period 200 10000 ns See note (1) TSCLKL SCLK low 80 ns TSCLKH SCLK high 80 ns Tgs Glitch suppression on SCLK input 18 29 ns TSSH SPI reset (/SS high) 50 ns TNCSL /SS falling to SCLK rising 25(2) ns First SCLK pulse TNCSH SCLK falling to /SS rising 80 ns Last SCLK pulse TDIS Data in setup time 10 ns TDIH Data in hold time 10 ns Read Timing (VP_IO= 3.3V, Temperature 25°C, Cload ≤ 50pF) TDOD Data out delay 20 ns TDOHZ Data out to high impedance delay 20 ns EEPROM Write Timing (VP_IO= 3.3V, Temperature 25°C) TEWS EEPROM write time via SPI 8.3 9.5 ms /SS rising edge to IRQ I_io_eewr |
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