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AMD8513 Datasheet(PDF) 65 Page - Infineon Technologies AG |
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AMD8513 Datasheet(HTML) 65 Page - Infineon Technologies AG |
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65 / 88 page  Data Sheet 65 Rev. 1.21, 2005-12-05 ADM8513 Data Sheet Registers Description The register is addressed wordwise. ANLPA Auto-Negotiation Link Partner Ability 5H 72 ANE Auto-Negotiation Expansion 6H 72 Table 73 Register Access Types Mode Symbol Description HW Description SW read/write rw Register is used as input for the HW Register is readable and writable by SW read r Register is written by HW (register between input and output -> one cycle delay) Value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= Target for development.) Read only ro Register is set by HW (register between input and output -> one cycle delay) SW can only read this register Read virtual rv Physically, there is no new register, the input of the signal is connected directly to the address multiplexer. SW can only read this register Latch high, self clearing lhsc Latch high signal at high level, clear on read SW can read the register Latch low, self clearing llsc Latch high signal at low-level, clear on read SW can read the register Latch high, mask clearing lhmk Latch high signal at high level, register cleared with written mask SW can read the register, with write mask the register can be cleared (1 clears) Latch low, mask clearing llmk Latch high signal at low-level, register cleared on read SW can read the register, with write mask the register can be cleared (1 clears) Interrupt high, self clearing ihsc Differentiate the input signal (low- >high) register cleared on read SW can read the register Interrupt low, self clearing ilsc Differentiate the input signal (high- >low) register cleared on read SW can read the register Interrupt high, mask clearing ihmk Differentiate the input signal (high- >low) register cleared with written mask SW can read the register, with write mask the register can be cleared Interrupt low, mask clearing ilmk Differentiate the input signal (low- >high) register cleared with written mask SW can read the register, with write mask the register can be cleared Interrupt enable register ien Enables the interrupt source for interrupt generation SW can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset Register is readable and writable by SW Read/write self clearing rwsc Register is used as input for the hw, the register will be cleared due to a HW mechanism. Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. Table 72 Registers Overview (cont’d) Register Short Name Register Long Name Offset Address Page Number |
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