LMX2572LP datasheet(28/82 Pages) TI1

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LMX2572LP

SNAS764 – MAY 2018

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7.6.11 Register R10 (offset = 0Ah) [reset = 10F8h]

Figure 38. Register R10

MULT

R/W-1h

R/W-78h

Table 17. Register R10 Field Descriptions

Bit

Field

Type Reset

Description

15 - 12

R/W

Program 1h to this field.

11 - 7

MULT

R/W

Reference path frequency Multiplier. Input frequency to the Multiplier: 10 to 40 MHz.

Multiplier output frequency: 60 to 150 MHz.

0: Not used

1: Bypassed

2: Not recommended. Use OSC_2X instead of MULT

3: 3X

·····

7: 7X

8 - 31: Not recommended

6 - 0

R/W

78h

Program 78h to this field.

7.6.12 Register R11 (offset = 0Bh) [reset = B018h]

Figure 39. Register R11

PLL_R

R/W-Bh

R/W-1h

R/W-8h

Table 18. Register R11 Field Descriptions

Bit

Field

Type Reset

Description

15 - 12

R/W

Program Bh to this field.

11 - 4

PLL_R

R/W

Reference path Post-R divider. It is the divider after the frequency Multiplier.

3 - 0

R/W

Program 8h to this field.

7.6.13 Register R12 (offset = 0Ch) [reset = 5001h]

Figure 40. Register R12

PLL_R_PRE

R/W-5h

R/W-1h

Table 19. Register R12 Field Descriptions

Bit

Field

Type Reset

Description

15 - 12

R/W

Program 5h to this field.

11 - 0

PLL_R_PRE

R/W

Reference path Pre-R divider. It is the divider before the frequency Multiplier.

7.6.14 Register R13 (offset = 0Dh) [reset = 4000h]

Figure 41. Register R13

R/W-4000h

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