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LMX2572LP Datasheet(PDF) 7 Page - Texas Instruments

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Part # LMX2572LP
Description  2-GHz Low Power Wideband RF Synthesizer With FSK Modulation
PDF  82 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMX2572LP Datasheet(HTML) 7 Page - Texas Instruments

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LMX2572LP
www.ti.com
SNAS764 – MAY 2018
Product Folder Links: LMX2572LP
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Electrical Characteristics (continued)
3.0 V
≤ VCC ≤ 3.5 V, –40°C ≤ TA ≤ 85°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PHASE SYNCHRONIZATION
fOSCinSYNC
OSCin input frequency with
SYNC
Category 3
5
100
MHz
Categories 1 and 2
5
200
|tskewSYNC|
OSCin to RFout skew
After phase synchronization;
fOSCinSYNC = fOUT = 100 MHz
2
ns
DIGITAL INTERFACE
VIH
High-level input voltage
1.4
VCC
V
VIL
Low-level input voltage
0.4
IIH
High-level input current
–25
25
µA
IIL
Low-level input current
–25
25
VOH
High-level output voltage
Load current = –5 mA
MUXout pin
VCC – 0.5
V
VOL
Low-level output voltage
Load current = 5 mA
0.5
6.6 Timing Requirements
3.0 V
≤ VCC ≤ 3.5 V, –40°C ≤ TA ≤ 85°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
MIN
NOM
MAX
UNIT
SERIAL INTERFACE WRITE TIMING
fSCK
SCK frequency
1 / (tCWL+tCWH)
75
MHz
tES
SCK to CSB low time
Figure 1
5
ns
tCS
SDI to SCK setup time
2
ns
tCH
SDI to SCK hold time
2
ns
tCWH
SCK pulse width high
5
ns
tCWL
SCK pulse width low
5
ns
tCES
CSB to SCK setup time
5
ns
tEWH
CSB pulse width high
2
ns
SERIAL INTERFACE READ TIMING
fSCK
SCK frequency
1 / (tCWL+tCWH)
50
MHz
tES
SCK to CSB low time
Figure 1
10
ns
tCS
SDI to SCK setup time
10
ns
tCH
SDI to SCK hold time
10
ns
tCWH
SCK pulse width high
10
ns
tCWL
SCK pulse width low
10
ns
tCES
CSB to SCK setup time
10
ns
tEWH
CSB pulse width high
10
ns
SYNC TIMING
tCS
Pin to OSCin setup time
Figure 2
2.5
ns
tCH
Pin to OSCin hold time
2
ns



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