LMX2572LP datasheet(68/82 Pages) TI1

68 / 82 page

LMX2572LP

SNAS764 – MAY 2018

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Product Folder Links: LMX2572LP

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To enable FSK I2S mode, set

•

INPIN_IGNORE = 0

•

FSK_MODE_SEL = 1 (FSK I2S)

•

FSK_EN = 1

8.1.9 Unused Pins

TI recommends to pull these pins low if they are not used:

•

Pin 5, SYNC

•

Pin 28, SysRefReq

•

Pin 30, RampClk

•

Pin 32, RampDir

8.1.10 External Loop Filter

The LMX2572LP requires an external loop filter that is application-specific and can be configured by PLLatinum

Sim. For the LMX2572LP, it matters what impedance is seen from the Vtune pin looking outwards. This

impedance is dominated by the component C3 for a third order filter or C1 for a second order filter. If there is at

least 1.5 nF for the capacitance that is shunt with this pin, the VCO phase noise will be close to the best it can

be. If there is less, the VCO phase noise in the 100-kHz to 1-MHz region will degrade. This capacitor should be

placed close to the Vtune pin.

Figure 167. External Loop Filter

8.1.11 Power-Up, Wake-Up Time

When the device comes out of the powered-down state, either by resuming the POWERDOWN bit to zero or by

pulling back CE pin HIGH (if it was powered down by CE pin), it takes time for the device to acquire lock again.

This wake-up time depends on LDO_DLY setting, loop bandwidth, and the state machine clock frequency (=

fOSCin / 2

CAL_CLK_DIV). If the loop bandwidth is greater than 20 kHz, the wake-up time could be adjusted to less

than 1.5 ms with the LDO_DLY setting listed in Table 141.

Table 141. LDO_DLY Setting

STATE MACHINE CLOCK

FREQUENCY

LDO_DLY

130 MHz

≤ f ≤ 200MHz

80 MHz

≤ f < 130 MHz

50 MHz

≤ f < 80 MHz

30 MHz

≤ f < 50 MHz

f < 30 MHz

LMX2572LP Datasheet(PDF) 68 Page - Texas Instruments

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