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IMX7SCEC Datasheet(PDF) 34 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 34 Figure 5. i.MX 7Solo power-down sequence 4.1.10 Power supplies usage I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package information and contact assignments.” 4.2 Integrated LDO voltage regulator parameters Various internal supplies can be powered from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX 7Solo Application Processor Reference Manual (IMX7SRM) for details on the power tree scheme. NOTE The *_CAP signals must not be powered externally. The *_CAP pins are for the bypass capacitor connection only. |
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