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IMX7SCEC Datasheet(PDF) 62 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 62 Page - NXP Semiconductors |
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62 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 62 Figure 26 shows the DDR3 read timing diagram. The timing parameters for this diagram appear in Table 42. Figure 26. DDR3 read cycle 1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P in the middle of DRAM_DATAxx window. 2 All measurements are in reference to Vref level. 3 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF. 4.8.4.2 LPDDR3 parameters Figure 27 shows the LPDDR3 basic timing diagram. The timing parameters for this diagram appear in Table 43. Figure 27. LPDDR3 command and address timing diagram Table 42. DDR3 read cycle ID Parameter Symbol CK = 533 MHz Unit Min Max DDR26 Minimum required DRAM_DATAxx valid window width — 510 — ps DRAM_SDCLKx_P DRAM_SDCLKx_N DRAM_SDQSx_P DRAM_DATAxx DATA DATA DATA DATA DATA DATA DATA DATA DDR26 (input) (input) |
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