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IMX7SCEC Datasheet(PDF) 117 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 117 Page - NXP Semiconductors |
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117 / 152 page ![]() Package information and contact assignments i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 117 6.1.2 12 x 12 mm supplies contact assignments and functional contact assignments Table 91 shows supplies contact assignments for the 12 x 12 mm package. Table 91. i.MX 7Solo 12 x 12 mm supplies contact assignments Supply Rail Ball(s) position(s) Remarks DRAM_VREF T20 DDR voltage reference input. Connect to a voltage source that is 50% of NVCC_DRAM DRAM_ZQPAD Y18 DDR output buffer driver calibration reference voltage input. Connect DRAM_ZQPAD to an external 240 ohm 1% resistor to Vss FUSE_FSOURCE V09 GND A01,A28,B05,B23,B26,C03,C05,C07,C10,C1 3,C14,C15,C23,C24,C25,C26,D08,D11,D17, D21,E03,E05,E24,E26,F08,F09,F10,F12,F14, F15,F17,F21,H04,H06,H23,H25,L13,L16,M04 ,M06,M23,M25,N11,N18,T11,T18,U04,U06,U 23,U25,V13,V16,W03,W06,Y16,AA04,AA06, AA23,AA25,AC08,AC10,AC12,AC14,AC15,A C17,AC21,AD03,AD05,AD06,AD24,AD26,AE 06,AE07,AE08,AE09,AE17,AE21,AF03,AF05, AF08,AF09,AF10,AF11,AF13,AF14,AF15,AF2 4,AF26,AG10,AH01,AH28 GPANAIO AF02 Test signal. Should be left unconnected. MIPI_VREG_0P4V B19 NVCC_DRAM V27,V28,W21,W23,W26,Y20,AA19,AC19,AF 17,AF18,AF19,AG18,AH18 Supply input for the DDR I/O interface NVCC_DRAM_CKE V20 NVCC_ENET1 J18 Supply input for the ENET interfaces NVCC_EPDC1 P20 Supply for EPDC NVCC_EPDC2 N20 Supply for EPDC NVCC_GPIO1 Y09 Supply for GPIO1 NVCC_GPIO2 Y11 Supply for GPIO2 NVCC_I2C R09 Supply for I2C NVCC_LCD L20 Supply for LCD NVCC_SAI J13 Supply for SAI NVCC_SD1 J11 Supply for SD card NVCC_SD2 L09 Supply for SD card NVCC_SD3 N09 Supply for SD card NVCC_SPI P09 Supply for SPI |
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