SC68C752B datasheet(9/49 Pages) PHILIPS

9 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

9 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.2.1 Auto-RTS

Auto-RTS data ﬂow control originates in the receiver block (see Figure 1 “Block diagram of

SC68C752B” on page 3). Figure 5 shows RTS functional timing. The receiver FIFO trigger

levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below

the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached,

RTS is de-asserted. The sending device (for example, another UART) may send an

additional byte after the trigger level is reached (assuming the sending UART has another

byte to send) because it may not recognize the de-assertion of RTS until it has begun

sending the additional byte. RTS is automatically reasserted once the receiver FIFO

reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows the

sending device to resume transmission.

Fig 4.

Auto ﬂow control (Auto-RTS and Auto-CTS) example

FIFO

FLOW

CONTROL

FIFO

PARALLEL

TO SERIAL

FIFO

UART 1

UART 2

D7 to D0

RTS

CTS

RTS

D7 to D0

002aaa228

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

Fig 5.

RTS functional timing

Start

byte N

Start

byte N

+ 1

Start

Stop

RTS

R/W

+ 1

002aab086

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