SC68C752B datasheet(14/49 Pages) PHILIPS

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SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

14 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5 Interrupts

The SC68C752B has interrupt generation and prioritization (six prioritized levels of

interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of

interrupts and the IRQ signal in response to an interrupt generation. The IER can also

disable the interrupt system by clearing bits 0:3, 5:7. When an interrupt is generated, the

IIR indicates that an interrupt is pending and provides the type of interrupt through

IIR[5:0]. Table 7 summarizes the interrupt control functions.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]

generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,

and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always

represent the error status for the received character at the top of the RX FIFO. Reading

the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of

the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff ﬂow character detection caused the interrupt, the interrupt

is cleared by an Xon ﬂow character detection. If a special character detection caused the

interrupt, the interrupt is cleared by a read of the IIR.

Table 7:

Interrupt control functions

IIR[5:0]

Priority

level

Interrupt type

Interrupt source

Interrupt reset method

000001

None

none

000110

receiver line status

OE, FE, PE, or BI errors occur in

characters in the RX FIFO

FE, PE, BI: all erroneous

characters are read from the

RX FIFO.

OE: read LSR

001100

RX time-out

stale data in RX FIFO

read RHR

000100

RHR interrupt

DRDY (data ready)

(FIFO disable)

RX FIFO above trigger level

(FIFO enable)

read RHR

000010

THR interrupt

TFE (THR empty)

(FIFO disable)

TX FIFO passes above trigger level

(FIFO enable)

read IIR or a write to the THR

000000

modem status

MSR[3:0] = 0

read MSR

010000

Xoff interrupt

receive Xoff character(s)/special

character

receive Xon character(s)/Read of

IIR

100000

CTS, RTS

RTS pin or CTS pin change state from

active (LOW) to inactive (HIGH)

read IIR

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