SC68C752B datasheet(23/49 Pages) PHILIPS

23 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

23 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting

transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 12

shows FIFO Control Register bit settings.

Table 12:

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB),

FCR[6] (LSB)

RX trigger. Sets the trigger level for the RX FIFO.

00 - 8 characters

01 - 16 characters

10 - 56 characters

11 - 60 characters

5:4

FCR[5] (MSB),

FCR[4] (LSB)

TX trigger. Sets the trigger level for the TX FIFO.

00 - 8 spaces

01 - 16 spaces

10 - 32 spaces

11 - 56 spaces

FCR[5:4] can only be modiﬁed and enabled when EFR[4] is set. This is

because the transmit trigger level is regarded as an enhanced function.

FCR[3]

DMA mode select.

logic 0 = Set DMA mode ‘0’

logic 1 = Set DMA mode ‘1’

FCR[2]

Reset TX FIFO.

logic 0 = No FIFO transmit reset (normal default condition)

logic 1 = Clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FCR[1]

Reset RX FIFO.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO

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