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DLPC6421

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DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Copyright © 2018, Texas Instruments Incorporated

Layout Guidelines (continued)

(1)

Line width is expected to be adjusted to achieve impedance requirements

Table 9. General PCB Routing (Applies to All Corresponding PCB Signals)

PARAMETER

APPLICATION

SINGLE-ENDED SIGNAL

DIFFERENTIAL PAIRS

UNIT

Escape Routing in Ball

Field

4 (0.1)

4 (0.1)

mil (mm)

PCB Etch Data or Control

7 (0.18)

4.25 (0.11)

mil (mm)

PCB Etch Clocks

7 (0.18)

4.25 (0.11)

mil (mm)

Minimum Line spacing to

other signals (S)

Escape Routing in Ball

Field

4 (0.1)

4 (0.1)

mil (mm)

PCB Etch Data or Control

10 (0.25)

20 (0.51)

mil (mm)

PCB Etch Clocks

20 (0.51)

20 (0.51)

mil (mm)

(1)

These values apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC6421

controller or the DMD. Additional margin can be attained if internal DLPC6421 package skew is taken into account.

(2)

To minimize EMI radiation, serpentine routes added to facilitate matching should be implemented on signal layers only, and between

reference planes.

SIGNAL GROUP LENGTH MATCHING

I/F

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD (LVDS)

SCA_P,SCA_N,

DDA_P(15:0),

DDA_N(15:0)

DCKA_P, DCKA_N

+/-150 (+/-3.81)

mil (mm)

DMD (LVDS)

SCB_P,SCB_N,

DDB_P(15:0),

DDB_N(15:0)

DCKB_P, DCKB_N

+/-150 (+/-3.81)

mil (mm)

Number of layer changes:

•

Single ended signals: Minimize

•

Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair

should not change layers.

Termination requirements:

•

DMD Interface: None, the DMD receiver is differentially terminated to 100 ohm internally

Connector (DMD-LVDS I/F bus only) - High Speed Connectors that meet the following requirements should

be used:

● Differential Crosstalk

<5 %

● Differential Impedance

75-125 ohms

Routing requirements for right angle connectors:

When using right angle connectors, P-N pairs should be routed in same row to minimize delay mismatch.

When using right angle connectors, propagation delay difference for each row should be accounted for on

associated PCB etch lengths.