Data Sheet

AD5683R/AD5682R/AD5681R/AD5683

Rev. D | Page 9 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

3

GND

4

SCLK

1

2

LDAC

6SDI

5 SYNC

AD5681R/

AD5682R/

AD5683R/

AD5683

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

Figure 6. Pin Configuration, 8-Lead LFCSP, LDAC Option

3

GND

4

SCLK

1

2

6SDI

5 SYNC

AD5683R-1/

AD5681R-1

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

3

GND

4

SCLK

1

2

RESET

6SDI

5SYNC

AD5683R-2

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

Figure 8. Pin Configuration, 8-Lead LFCSP, RESET Option

Table 7. Pin Function Descriptions, 8-Lead LFCSP

Pin No.

Mnemonic

Description

LDAC

RESET

1

1

1

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.

2

N/A

N/A

LDAC

LDAC can be operated in asynchronous mode (see Figure 4). Pulsing this pin low allows the DAC

register to be updated if the input register has new data. This pin can be tied permanently low; in

this case, the DAC is automatically updated when new data is written to the input register.

N/A

2

N/A

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.

N/A

N/A

2

RESET

Asynchronous Reset Input. The RESET input is low level sensitive. When RESET is low, all LDAC pulses

are ignored, the input and DAC registers are at their default values, and the output is connected to

3

3

3

GND

Ground Reference Point for All Circuitry on the Device.

4

4

4

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz.

5

5

5

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC

goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data is

transferred in on the falling edges of the next 24 clocks.

6

6

6

SDI

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.

7

7

7

AD5683R/AD5682R/AD5681R Reference Output. When using the internal reference, this is the

reference output pin. The default for this pin is as a reference output. It is recommended that this

pin be decoupled to GND with a 10 nF capacitor.

8

8

8

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

0

0

0

EPAD

Exposed Pad. Connect the exposed pad to GND.