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AD5683RARMZ Datasheet(PDF) 23 Page - Analog Devices |
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AD5683RARMZ Datasheet(HTML) 23 Page - Analog Devices |
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23 / 28 page ![]() Data Sheet AD5683R/AD5682R/AD5681R/AD5683 Rev. D | Page 23 of 28 INTERNAL REGISTERS Input Shift Register The shift register of the AD5683R/AD5682R/AD5681R/AD5683 is 24 bits wide. Serial data is loaded MSB first (DB23) and the first four bits are the command bits, C3 to C0, followed by the data bits. The data bits comprise a 20-bit, 18-bit, or 16-bit input code, followed by a number of don’t care bits as shown in Table 9. The command is decoded on the rising edge of SYNC. Input Register The input register acts as a buffer to preload new data. This register does not control the voltage in the VOUT pin. There are two different ways to transfer the contents of the input register to the DAC register: by software or by hardware. DAC Register The DAC register controls the voltage in the VOUT pin. This register can be updated by issuing a command or by transferring the contents of the input register to the DAC register. COMMANDS Write Input Register The input register allows the preloading of a new value for the DAC register. The transfer from the input register to the DAC register can be triggered by hardware, by the LDAC pin, or by software using Command 2. If new data is loaded into the DAC register directly using Command 3, the DAC register automatically overwrites the input register. Update DAC Register This command transfers the contents of the input register to the DAC register and, consequently, the VOUT pin is updated. This operation is equivalent to a software LDAC. Write DAC Register The DAC register controls the output voltage in the DAC. This command updates the DAC register on completion of the write operation. The input register is refreshed automatically with the DAC register value. Table 9. Command Operation Command [DB23:DB20] Data Bits [DB19:DB0]1 Operation C3 C2 C1 C0 DB19 DB18 DB17 DB16 DB15 DB14 [DB13:DB8] DB7 DB6 DB5 DB4 [DB3:DB0] 0 0 0 0 X X X X X X X…X X X X X X…X Do nothing 0 0 0 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9…DB4 DB32 DB22 DB12,3 DB02,3 X…X Write input register 0 0 1 0 X X X X X X X…X X X X X X…X Update DAC register (software LDAC) 0 0 1 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9…DB4 DB32 DB22 DB12,3 DB02,3 X…X Write DAC and input register 0 1 0 0 DB19 DB18 DB17 DB16 DB15 DB14 0…0 0 0 0 0 0…0 Write control register 0 1 0 1 X X X X X X X…X X X X X X…X Readback input register 1 X means don’t care. 2 This bit is a don’t care bit for the AD5681R only. 3 This bit is a don’t care bit for the AD5682R only. |
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