AD5683RARMZ datasheet(21/28 Pages) AD

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Data Sheet

AD5683R/AD5682R/AD5681R/AD5683

Rev. D | Page 21 of 28

SERIAL INTERFACE

The AD5683R/AD5682R/AD5681R/AD5683 uses a 3-wire

serial interface that is compatible with some SPI modes, Mode 1

and Mode 2, as well as with completely synchronous interfaces

such as SPORT. See Figure 4 for a timing diagram of a typical

write sequence. See the AN-1248 Application Note for more

information about the SPI interface.

SPI SERIAL DATA INTERFACE

Pulling low SYNC pin, the internal input shift register is

enabled, the data in the SDI pin is sampled into the input shift

held low until the complete data-word (24-bits) is loaded from

the SDI pin (see Figure 4). When SYNC returns high, the serial

data-word is decoded, following the instructions in Table 9.

Between consecutive data-words, SYNC must be held high for a

minimum of 20 ns. Between consecutive DAC updates, SYNC

must be held high for more than 20 ns to satisfy the DAC

update condition as shown in Figure 4.

If SYNC is brought high after 24 falling clock edges, it is interpreted

as a valid write, and the first 24 bits are loaded to the input shift

To minimize power consumption, it is recommended that all

serial interface pins be operated close to the supply rails.

SHORT WRITE OPERATION (AD5681R ONLY)

The AD5681R SPI serial interface allows data to be transferred

using a smaller number of clocks, if required. The last eight bits

are don’t care bits if the input or DAC registers are written as

shown in Table 9. To increase the DAC update rate, the size of

the data-word can be reduced.

If SYNC is brought high between 16 and 24 clock edges, this is

interpreted as a valid write and only the first 16 bits are decoded,

as shown in Figure 49. If SYNC is brought high before 16 falling

clock edges, the serial write is ignored and the write sequence is

considered invalid. If the DCEN bit is enabled, this functionality

is not available (see Table 11).

SDO Pin

The serial data output pin (SDO), which is available only in the

AD5683R, serves two purposes: to read back the contents of the

DAC registers and to connect the device in daisy-chain mode.

The SDO pin contains a push-pull output that internally includes

a weak pull-down resistor. The data is clocked out of SDO on

the rising edge of SCLK, as shown in Figure 4, and the pin is

active only when the DCEN bit is enabled in the write control

standby mode, the internal pull-down resistor forces a Logic 0 on

the bus. Due to the high value of the internal pull-down resistor,

other devices can have control over the SDO line if a parallel

connection is made.

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

SDI

SYNC

SCLK

Figure 49. Short Write on the AD5681R

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