AD5683RARMZ datasheet(24/28 Pages) AD

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AD5683R/AD5682R/AD5681R/AD5683

Data Sheet

Rev. D | Page 24 of 28

Write Control Register

The write control register sets the power-down and gain

functions. It also enables/disables the internal reference and

perform a software reset. See Table 10 for the write control

Table 10. Write Control Register Bits

DB19

DB18

DB17

DB16

DB15

DB14

Reset

PD1

PD0

REF

Gain

DCEN

DCEN Bit

The daisy-chain enable bit (DCEN, Bit DB14) enables the SDO pin,

allowing the device to operate in daisy-chain mode. This bit is

automatically disabled when a readback command is executed.

Enabling this bit disables the write short command feature in the

AD5681R.

Table 11. Daisy-Chain Enable Bit (DCEN)

DB0

Mode

Standalone mode (default)

DCEN mode

Gain Bit

The gain bit selects the gain of the output amplifier. Table 12

shows how the output voltage range corresponds to the state of

the gain bit.

Table 12. Gain Bit

Gain

Output Voltage Range

0 V to VREF (default)

0 V to 2 × VREF

REF Bit

The on-chip reference is on at power-up by default. This reference

can be turned on or off by setting a software-programmable bit,

DB16, in the write control register. Table 13 shows how the state

of the bit corresponds to the mode of operation.

To reduce the power consumption, it is recommended to

disable the internal reference if the device is placed in power-

down mode.

Table 13. Reference Bit (REF)

REF

Reference Function

Reference enabled (default)

Reference disabled

PD0 and PD1 Bits

The AD5683R/AD5682R/AD5681R contain two separate mode of

operation that are accessed by writing to the write control register.

In normal mode, the output buffer is directly connected to the

VOUT pin.

In power-down mode, the output buffer is internally disabled

and the VOUT pin output impedance can be selected to a well-

known value, as shown in Table 14.

Table 14. Operation Modes

Operating Mode

PD1

PD0

Normal Mode

Power-Down Modes

1 kΩ Output Impedance

100 kΩ Output Impedance

Three-State Output Impedance

In power-down mode, the device disables the output buffer but

does not disable the internal reference. To achieve maximum

power savings, it is recommend to disable the REF bit, if

possible.

Disabling both the internal reference and the output buffer

results in the supply current falling to 2 μA at 5 V.

The output stage is shown in Figure 52.

RESISTOR

NETWORK

VOUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 52. Output Stage During Power-Down

The output amplifier is shut down when the power-down mode

is activated. However, unless the internal reference is powered

down (using Bit DB16 in the write control register), the bias

generator, reference, and resistor string remain on. When in

power-down mode, the weak SDO resistor is also disconnected.

The supply current falls to 2 μA at 5 V. The contents of the DAC

exit power-down is typically 4 μs for VDD = 5 V, or 600 μs if the

reference is disabled.

Reset Bit

The write control register of the AD5683R/AD5682R/AD5681R

contains a software reset function that resets the input and DAC

registers to zero scale and resets the write control register to the

default value. A software reset is initiated by setting the reset bit

(Bit DB19) in the write control register to 1. When the software

reset is complete, the reset bit is cleared to 0 automatically.

AD5683RARMZ Datasheet(PDF) 24 Page - Analog Devices

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