AD5683RARMZ datasheet(26/28 Pages) AD

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AD5683R/AD5682R/AD5681R/AD5683

Data Sheet

Rev. D | Page 26 of 28

THERMAL HYSTERESIS

Thermal hysteresis is the voltage difference induced on the

reference voltage by sweeping the temperature from ambient

to cold, to hot, and then back to ambient.

The thermal hysteresis data is shown in Figure 54. It is measured by

sweeping the temperature from ambient to −40°C, then to +105°C,

and finally returning to ambient. The VREF delta is next measured

between the two ambient measurements; the result is shown in a

solid line in Figure 54. The same temperature sweep and measure-

ments were immediately repeated; the results are shown in a

patterned line in Figure 54.

–100

–20

–60

–40

–80

DISTORTION (ppm)

FIRST TEMPERATURE SWEEP

SUBSEQUENT…

Figure 54. Thermal Hysteresis

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at the

digital pins and analog pins, it is important to power GND first

before applying any voltage to VDD, VOUT, and VLOGIC. Otherwise,

the diode is forward-biased such that VDD is powered uninten-

tionally. The ideal power-up sequence is GND, VDD, VLOGIC,

VREF, followed by the digital inputs.

RECOMMENDED REGULATOR

The AD5683R/AD5682R/AD5681R/AD5683 use a 5 V (VDD)

supply as well as a digital logic supply (VLOGIC).

The analog and digital supplies required for the AD5683R/

AD5682R/AD5681R/AD5683 can be generated using Analog

Devices, Inc., low dropout (LDO) regulators such as the ADP7118

and the ADP162, respectively, for analog and digital supplies.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration of

the power supply and ground return layout helps to ensure the

rated performance. The printed circuit board (PCB) on which the

ADCs are mounted must be designed such that the AD5683R/

AD5682R/AD5681R/AD5683 lie on the analog plane.

Ensure that the AD5683R/AD5682R/AD5681R/AD5683 have

ample supply bypassing of 10 µF, in parallel with a 0.1 µF capacitor

on each supply that is located as near to the package as possible

(ideally, right up against the device). The 10 µF capacitors are

of the tantalum bead type. The 0.1 µF capacitor must have

low effective series resistance (ESR) and low effective series

inductance (ESI), such as the common ceramic types, which

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

In systems where there are many devices on one board, it is

often useful to provide some heat sinking capability to allow

the power to dissipate easily.

The LFCSP packages of the AD5683R/AD5682R/AD5681R/

AD5683 have an exposed pad beneath the device. Connect this

pad to the GND supply of the device. For optimum performance,

use special consideration when designing the motherboard and

mounting the package. For enhanced thermal, electrical, and

board level performance, solder the exposed pad on the bottom

of the package to the corresponding thermal land pad on the

PCB. Design thermal vias into the PCB land pad area to further

improve heat dissipation.

The GND plane on the device can be increased (as shown in

Figure 55) to provide a natural heat sinking effect.

AD5683R/

AD5682R/

AD5681R/

AD5683

GND

PLANE

BOARD

Figure 55. Pad Connection to Board

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