CF52012 datasheet(18/48 Pages) INTEL

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Table 14.

Status Register Bits

Bit

R/W

Default

Value

Name

Value

Description

R/W

None

R/W

BP3 (Block

Protect Bit)(9)

(10)

Table 15 on page 19 through Table 26 on page

24 list the protected area with reference to

the block protect bits.

Determine the area of

the memory protected

from being written or

erased unintentionally.

R/W

TB (Top/Bottom

Bit)

• 1=Protected area starts from the bottom of

the memory array.

• 0=Protected area starts from the top of the

memory array.

Determine that the

protected area starts

from the top or

bottom of the memory

array.

R/W

BP2(9)

Table 15 on page 19 through Table 26 on page

24 list the protected area with reference to

the block protect bits.

Determine the area of

the memory protected

from being written or

erased unintentionally.

BP1(9)

BP0(9)

WEL (Write

Enable Latch

Bit)

• 1=Allows the following operation to run:

— Write Bytes

— Write Status Register

— Erase Bulk

— Erase Die

— Erase Sector

• 0=Rejects the above mentioned operations.

Allows or rejects

certain operation to

run.

WIP (Write in

Progress Bit)

• 1=One of the following operation is in

progress:

— Write Status Register

— Write NVCR

— Write Bytes

— Erase

• 0=no write or erase cycle in progress

Indicates if there is a

command in progress.

1.6.1.1. Read Status Register Operation (05h)

Figure 1.

Read Status Operation Timing Diagram

nCS

DCLK

DATA0

DATA

Operation Code (05h)

MSB

Status Register Out

High Impedance

(9) The erase bulk and erase die operation is only available when all the block protect bits are set

to 0. When any of the block protect bits are set to 1, the relevant area is protected from being

written by a write bytes operation or erased by an erase sector operation.

(10) Applicable for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices only.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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